TLC5948APWPR datasheet(29/54 Pages) TI2

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Lower 137 Bits

Second Control Data Latch (119 Bits)

7 Bits

112 Bits

13-7

20-14

27-21

97-91

104-98

111-105

MSB

118-112

90-84

Bits[6:0]

for OUTn

Global Brightness

Control Circuit

Dot Correction

Circuit

LSB

6-0

Bits[6:0]

OUT15

Bits[6:0]

OUT12

Bits[6:0]

OUT13

Bits[6:0]

OUT14

Bits[6:0]

OUT3

Bits[6:0]

OUT2

Bits[6:0]

OUT1

Bits[6:0]

OUT0

BC,

7 Bits

DC, 112 Bits

First Control Data Latch (137 Bits)

18 Bits

MSB

136-119

13-7

20-14

27-21

97-91

104-98

111-105

118-112

FC,

18 Bits

90-84

Bits

17-0

Bits[6:0]

for OUTn

Function

Control Circuit

LSB

6-0

Bits[6:0]

OUT15

Bits[6:0]

OUT12

Bits[6:0]

OUT13

Bits[6:0]

OUT14

Bits[6:0]

OUT3

Bits[6:0]

OUT2

Bits[6:0]

OUT1

Bits[6:0]

OUT0

BC,

7 Bits

DC, 112 Bits

119 Bits

From Common Shift Register

This latch pulse comes

from the LAT pin when

the MSB of the Common

Shift Register is ‘1’.

The 65,536th GSCLK is used

to latch the data when the

Auto Display Repeat is

enabled or when the BLANK bit

is set to ‘1’.

TLC5948A

www.ti.com

SBVS192A – MARCH 2012 – REVISED DECEMBER 2012

First and Second Control Data Latch

The first and second control data latches are 137 bits and 119 bits long, respectively. The first latch contains dot

correction (DC) data, global brightness control (BC) data, and function control (FC) data; the second latch

contains DC data and global BC data. The DC for each constant-current output and the BC for all constant-

current outputs are controlled by the second control data latch. The control data in the first latch are set by the

least significant 137 bits from the common shift register at the LAT rising edge when the common shift register

MSB is '1'. The 119 bits of DC and BC data from the first control data latch are copied to the second latch when

the 65,536th GSCLK occurs or when the BLANK bit in the first control data latch is set to '1'.

When the device is powered up, the data in the first latch (except the BLANK and PSMODE bits of the FC bits)

and second latch are random. Therefore, DC, BC, and FC data must be written to the first and second control

data latches before turning on the constant-current outputs. The default value of the BLANK bit is '1'. The first

and second control data latch configurations are shown in Figure 32.

Figure 32. First and Second Control Data (DC, BC, and FC) Latch Configuration

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