TMDS181RGZRG4 datasheet(13/60 Pages) TI2

13 / 60 page

TMDS181, TMDS181I

www.ti.com

SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017

Product Folder Links: TMDS181

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(1)

The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

(2)

The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.10 TMDS Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

REDRIVER MODE

Data rate (redriver mode)

250

3400

Mbps

tPLH

Propagation delay time (low to

high)

250

600

tPHL

Propagation delay time (high to

low)

250

800

tT1(1.4b)

Transition time (rise and fall

time); measured at 20% and

80% levels for data lanes.

TMDS clock meets tT3 for all

three times.

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; 1.48 Gbps and 2.97 Gbps data

lines, 148 MHz and 297 MHz clock

tT3

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; 1.48 Gbps, 2.97 Gbps

100

tSK_INTRA

Intra-pair output skew

Default setting for internal intra-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps; See Figure 8

tSK_INTER

Inter-pair output skew

Default setting for internal inter-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps; See Figure 8

100

tJITD1(1.4b)

Total output data jitter

HDMI1.4b

DR = 2.97 Gbps, PRE_SEL = NC,

EQ_SEL/A0 = NC ; . See Figure 12 at

TTP3

0.2

Tbit

tJITC1(1.4b)

Total output clock jitter

CLK = 25 MHz, 74.25 MHz, 75 MHz, 150

MHz, 297 MHz

0.25

Tbit

RETIMER MODE

Data rate (retimer mode)

0.25

Gbps

dXVR

Automatic redriver to retimer

crossover (when selected)

Measured with input signal applied = 200

mVpp

0.75

1.25

Gbps

fCROSSOVER

Crossover frequency hysteresis

250

MHz

PLLBW

Data retimer PLL bandwidth

Default loop bandwidth setting

0.4

MHz

tACQ

Input clock frequency detection

and retimer acquisition time

180

µs

IJT1

Input clock jitter tolerance

Tested when data rate >1.0Gbps

0.3

Tbit

tT1(2.0)

Transition time (rise and fall

time); measured at 20% and

80% levels for data lanes.

TMDS clock meets tT3 for all

three times.

TX_TERM_CTL = L; PRE_SEL = NC; 6

Gbps data lines,

tT1 (1.4b)

TX_TERM_CTL = NC; PRE_SEL = NC;

1.48 Gbps and 2.97 Gbps data lines, 148

MHz and 297 MHz clock

tT3

TX_TERM_CTL = NC; PRE_SEL = NC;

1.48 Gbps, 2.97 Gbps, 6 Gbps data lines,

148 MHz, 297 MHz clock

100

tDCD

OUT_CLK ± duty cycle

40%

50%

60%

tSK_INTER

Inter-pair output skew

Default setting for internal inter-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data

lines, 148 MHz, 297 MHz clock; See

Figure 8

0.2

Tch

tSK_INTRA

Intra-pair output skew

Default setting for internal intra-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data

lines, 148 MHz, 297 MHz clock; See

Figure 8

0.15

Tbit

tJITC1(1.4b)

Total output clock jitter

CLK = 25 MHz, 74.25 MHz, 75 MHz, 150

MHz, 297 MHz

0.25

Tbit

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