ADAQ4216BBCZ datasheet(12/65 Pages) AD

12 / 65 page

Data Sheet

ADAQ4216

SPECIFICATIONS

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Rev. B | 12 of 65

Table 6. Echo-Clock Mode Timing, DDR, 1-Lane

Parameter

Symbol

Min

Typ

Max

Unit

SCK Period

tSCK

12.3

SCK Low Time, SCK High Time

tSCKL, tSCKH

5.2

SCK Edge to Data/SCKOUT Remains Valid

tHSDO

1.1

SCK Edge to Data/SCKOUT Valid Delay

tDSDO

VIO > 1.71V

6.2

VIO > 1.14V

8.7

CS Falling Edge to First SCK Rising Edge

tCSSCK

12.3

Skew Between Data and SCKOUT

tSKEW

−0.4

+0.4

Last SCK Edge to CS Rising Edge

tSCKCS

CS Rising Edge to SDO High Impedance

tCSDIS

Figure 8. Echo-Clock Mode Timing, DDR, 1-Lane

Table 7. Host-Clock Mode Timing

Parameter

Symbol

Min

Typ

Max

Unit

SCK Period

tSCKOUT

OSC_DIV = No Divide

11.8

12.5

13.3

OSC_DIV = Divide by 2

23.6

26.6

OSC_DIV = Divide by 4

47.4

53.2

SCK Low Time

tSCKOUTL

0.45 × tSCKOUT

0.55 × tSCKOUT

SCK High Time

tSCKOUTH

0.45 × tSCKOUT

0.55 × tSCKOUT

CS Falling Edge to First SCKOUT Rising Edge

tDSCKOUT

VIO > 1.71V

13.6

VIO > 1.14V

Skew Between Data and SCKOUT

tSKEW

−0.4

+0.4

Last SCKOUT Edge to CS Rising Edge

tSCKOUTCS

5.2

CS Rising Edge to SDO High Impedance

tCSDIS

Figure 9. Host-Clock Mode Timing, SDR, 1-Lane

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