ADAQ4216BBCZ datasheet(2/65 Pages) AD

2 / 65 page

Data Sheet

ADAQ4216

TABLE OF CONTENTS

analog.com

Rev. B | 2 of 65

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................4

Specifications........................................................ 5

Timing Specifications......................................... 8

Absolute Maximum Ratings.................................14

Thermal Resistance......................................... 14

Electrostatic Discharge (ESD) Ratings.............14

ESD Caution.....................................................14

Pin Configurations and Function Descriptions.....15

Typical Performance Characteristics................... 17

Terminology......................................................... 30

Theory of Operation.............................................32

Overview.......................................................... 32

Transfer Function............................................. 32

Signal Chain Operation.................................... 33

Digital Sample Processing Features................ 33

Applications Information...................................... 35

Typical Application Diagram............................. 35

Reference Circuitry Design ............................. 40

ADC Reset....................................................... 41

Power Supplies................................................ 41

Serial Interface.................................................... 43

SPI Signals.......................................................43

Sample Conversion Timing and Data

Transfer.......................................................... 45

Clocking Modes ...............................................46

Data Clocking Requirements and Timing.........49

Layout Guidelines................................................54

Registers............................................................. 55

Interface Configuration A Register................... 56

Interface Configuration B Register................... 56

Device Configuration Register..........................57

Chip Type Register...........................................57

Product ID Low Register.................................. 57

Product ID High Register..................................57

Chip Grade Register.........................................58

Scratch Pad Register....................................... 58

SPI Revision Register...................................... 58

Vendor ID Low Register................................... 59

Vendor ID High Register...................................59

Stream Mode Register..................................... 59

Interface Status A Register.............................. 59

EXIT Configuration Mode Register...................60

Averaging Mode Register.................................60

Offset Registers................................................60

Gain Registers..................................................61

Modes Register................................................ 61

Internal Oscillator Register............................... 62

Output Driver Register......................................62

Test Pattern Registers...................................... 63

Digital Diagnostics Register............................. 64

Digital Errors Register...................................... 64

Outline Dimensions............................................. 65

Ordering Guide.................................................65

Evaluation Boards............................................ 65

REVISION HISTORY

7/2025—Rev. A to Rev. B

Changes to Transition Noise Parameter and Noise Spectral Density (NSD) Parameter; Table 1................... 5

Changes to Figure 11.....................................................................................................................................15

Changes to Figure 19 and Figure 22............................................................................................................. 18

Changes to Figure 24 through Figure 29....................................................................................................... 19

Added Figure 84 and Figure 85; Renumbered Sequentially..........................................................................29

Added Least Significant Bit (LSB) Section.....................................................................................................30

Added Transition Noise Section.....................................................................................................................30

Change to Transient Response Section........................................................................................................ 30

Changes to Common-Mode Rejection Ratio (CMRR) Section...................................................................... 30

Change to Power-Supply Rejection Ratio (PSRR) Section........................................................................... 30

Changes to Figure 91.................................................................................................................................... 35

5/2025—Rev. 0 to Rev. A

Change to Features Section............................................................................................................................ 1

Changes to Input Bias Current Parameter and Input Offset Current Parameter, Table 1................................ 5

Changes to Figure 61 and Figure 64............................................................................................................. 25

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