5.6 Timing Requirements

Minimum and Maximum specifications apply from TA of −10°C to 85°C. Typical specifications are at 25°C and VPUP = 3.3V

and 5V (unless otherwise noted).

MIN

NOM

MAX

UNIT

I/O PIN: GENERAL DATA

tSTARTUP

Start-up time

Minimum time SDQ must be HIGH before

device responds with a presence pulse

10

ms

tREC

Recovery Time

Standard speed(1) (2)

5

µs

Overdrive speed(1) (2)

5

µs

tREH

Rising-Edge Hold-Off Time

Standard speed(1) (2)

0.5

5

µs

tSLOT

Time Slot Duration

Standard speed(3)

65

µs

Overdrive speed(3)

11

µs

I/O PIN: SINGLE-WIRE RESET, PRESENCE-DETECT CYCLE

tRSTL

Reset Low Time

Standard speed

480

550

µs

Overdrive speed

48

80

µs

tPDH

Presence-Detect High Pulse

Standard speed

15

60

µs

Overdrive speed

2

6

µs

tPDL

Presence-Detect Low Time

Standard speed

60

240

µs

Overdrive speed

8

24

µs

tPDS

Presence-Detect Sample

Time (4),(5)

Standard speed

60

70

75

µs

Overdrive speed

6

8.7

10

µs

IO PIN: SINGLE-WIRE WRITE

tW0L

Write-Zero Low Time

Standard speed(6)

60

120

µs

Overdrive speed(6)

5

15.5

µs

tW1L

Write-One Low Time

Standard speed(6)

1

15

µs

Overdrive speed(6)

1

2

µs

IO PIN: SINGLE-WIRE READ

tRL

Read Low Time

Standard speed(2) (7)

5

15 - tRC

µs

Overdrive speed(2) (7)

1

2 - tRC

µs

tRDS

Read Sample Time (8)

Standard speed(2) (7)

tRL + tRC

15

µs

Overdrive speed(2) (7)

tRL + tRC

3

µs

FRAM

NCY

Write/Erase Cycles

(Endurance)(2)

1 million

Cycles

tPROG

Programming Time(2)

For all 63.25Kb of memory

1

ms

tDR

Data Retention(9)

At 70°C

10

Years

(1)

Ensure that the voltage on SDQ is less or equal to VILMAX at all times when the host is driving SDQ to a logic 0 level.

(2)

Specified by design, characterization or simulation only. Not production tested.

(3)

Defines maximum possible bit rate.

(4)

Interval after tRSTL during which a bus host can read logic 0 on SDQ if a TMF0064 is present. The presence detect pulse can be

outside this interval, but is complete within 2ms after power-up. This behavior addresses the scenario where the one-wire device has

been powered off (bus low) for a long time. Bus power is then applied. The device is allowed to malfunction, and generate a presence

pulse that violates the presence timing specification. However, the abnormal condition is resolved typically within 10ms.

(5)

System requirement.

(6)

tε in Figure 6-18 and Figure 6-19 represents the time required for the pullup circuitry to raise the voltage on the SDQ pin from VIL to

VTH. Hence the actual maximum duration for the host to pull the line low is tW1LMAX + tF – tε and tW0LMAX + tF – tε, respectively.

(7)

tRC in Figure 6-20 represents the time required for the pullup circuitry to raise the voltage on the SDQ pin from VIL to the input-high

threshold of the host device. Hence, the actual maximum duration for the host to pull the line low is tRLMAX + tF.

(8)

Refers to the minimum time after which the recognition of negative edge is possible after VTH has been reached on the preceding

rising edge.

(9)

Data retention time is degraded as TA increases. Long-term storage at elevated temperatures is not recommended.

TMF0064

SLVSJQ6 – SEPTEMBER 2025

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