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TMS320F28030 Datasheet(PDF) 22 Page - Texas Instruments |
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TMS320F28030 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 175 page  6.5 Power Consumption Summary 6.5.1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT MODE TEST CONDITIONS VREG ENABLED VREG DISABLED IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2) TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX Operational (Flash) The following peripheral clocks are enabled: • ePWM1/2/3/4/5/6/7 • eCAP1 • eQEP1 • eCAN • LIN • CLA • HRPWM • SCI-A • SPI-A/B • ADC • I2C • COMP1/2/3 • CPU-TIMER0/1/2 All PWM pins are toggled at 60 kHz. All I/O pins are left unconnected.(4) (6) Code is running out of flash with 2 wait states. XCLKOUT is turned off. 114 mA(7) 135 mA(7) 14 mA 18 mA 101 mA(7) 120 mA(7) 14 mA 18 mA 14 mA 18 mA IDLE Flash is powered down. XCLKOUT is turned off. All peripheral clocks are turned off. 13 mA 23 mA 10 μA 15 μA 13 mA 24 mA 120 μA 400 μA 10 μA 15 μA STANDBY Flash is powered down. Peripheral clocks are off. 4 mA 9 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA HALT Flash is powered down. Peripheral clocks are off. Input clock is disabled.(5) 46 μA 10 μA 15 μA 30 μA 24 μA 10 μA 15 μA (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. (3) The TYP numbers are applicable over room temperature and nominal voltage. (4) The following is done in a loop: • Data is continuously transmitted out of SPI-A/B, SCI-A, eCAN, LIN, and I2C ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • COMP1/2 are continuously switching voltages. • GPIO17 is toggled. (5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. (6) CLA is continuously performing polynomial calculations. (7) For F2803x devices that do not have CLA, subtract the IDD current number for CLA (see Table 6-1) from the IDD (VREG disabled)/IDDIO (VREG enabled) current numbers shown in Section 6.5.1 for operational mode. TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032 TMS320F28032-Q1, TMS320F28033, TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1 TMS320F28035, TMS320F28035-Q1 SPRS584Q – APRIL 2009 – REVISED JANUARY 2024 www.ti.com 22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TMS320F28030 TMS320F28030-Q1 TMS320F28031 TMS320F28031-Q1 TMS320F28032 TMS320F28032-Q1 TMS320F28033 TMS320F28033-Q1 TMS320F28034 TMS320F28034-Q1 TMS320F28035 TMS320F28035-Q1 |
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