8.2.1.3 Application Curves

Figure 8-3. Typical WDI Pulse

Figure 8-4. Watchdog Timeout Fault

8.3 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.04V and 6V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1µF capacitor between the VDD pin and the GND pin.

8.4 Layout

8.4.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a 0.1µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the

CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1µF ceramic capacitor as near as possible to the VDD pin.

• Place CCRST capacitor as close as possible to the CRST pin.

• Place CCWD capacitor as close as possible to the CWD pin.

• Place the pullup resistor on the RESET pin as close to the pin as possible.

TPS35-Q1

SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024

www.ti.com

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