6.7 Switching Characteristics

At 1.04V ≤ VDD ≤ 6V, MR = Open, RESET pull-up resistor (Rpull-up) = 100kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100kΩ

to VDD, output RESET / WDO load (CLOAD) = 10pF and over operating free-air temperature range –40℃ to 125℃, unless

otherwise noted. VDD ramp rate ≤ 1V/µs. Typical values are at TA = 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSTRT

Startup delay(2)

500

µs

tP_HL

RESET detect delay for VDD falling below

VIT–

VDD: (VIT+ + 10%) to (VIT– – 10%)

(1)

30

50

µs

tSD

Watchdog startup delay

Orderable part number TPS35xA,

TPS35xG

0

ms

Orderable part number TPS35xB,

TPS35xH

180

200

220

Orderable part number TPS35xC,

TPS35xI

450

500

550

Orderable part number TPS35xD,

TPS35xJ

0.9

1

1.1

s

Orderable part number TPS35xE,

TPS35xK

4.5

5

5.5

Orderable part number TPS35xF,

TPS35xL

9

10

11

tD

Reset time delay (3)

Orderable part number

TPS35xxxxxxB

1.6

2

2.4

ms

Orderable part number

TPS35xxxxxxC

9

10

11

ms

Orderable part number

TPS35xxxxxxD

22.5

25

27.5

ms

Orderable part number

TPS35xxxxxxE

45

50

55

ms

Orderable part number

TPS35xxxxxxF

90

100

110

ms

Orderable part number

TPS35xxxxxxG

180

200

220

ms

Orderable part number

TPS35xxxxxxH

0.9

1

1.1

s

Orderable part number

TPS35xxxxxxI

9

10

11

s

tWDO

Watchdog timeout delay

tD

s

t MR_RES

Propagation delay from MR low to reset

assertion

VDD ≥ VIT– + 0.2V,

MR = V MR_H to V MR_L

100

ns

t MR_tD

Delay from MR release to reset deassert

VDD = 3.3V,

MR = V MR_L to V MR_H

tD

s

(1)

tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS

(2)

Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is

deasserted after the startup delay (tSTRT) + tD delay.

(3)

VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)

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TPS35-Q1

SLVSGE8B – NOVEMBER 2022 – REVISED AUGUST 2024

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