ADPL12005/ADPL12006

20V, 5A/6A Fully Integrated Synchronous Buck

Converters

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Analog Devices | 10

Detailed Description

The ADPL12005/ADPL12006 ICs are small, synchronous buck converters with integrated high-side and low-side

switches. These ICs are designed to deliver up to 6A with input voltages from 3V to 20V while using only 20μA quiescent

current at no load (VSUP = 12V, VOUT = 3.3V). Voltage quality can be monitored by observing the PGOOD signal.

The ICs can operate in dropout mode by running at a very high-duty cycle, making them ideal for factory automation

applications.

The ADPL12005/ADPL12006 ICs offer an adjustable output voltage using an external resistor-divider. The frequency is

internally fixed at 400kHz and 1.5MHz, allowing for small external components and reduced output ripple. The device

automatically enters skip mode (SYNC pin pulled low) at light loads with an ultra-low-quiescent current of 20μA at no load.

The architecture is an average current-mode control that allows much better noise rejection of the current loop. The ICs

have a small minimum ON time of 36ns to allow for large step-down ratios in a single stage without skipping cycles.

The devices can also be used in a dual-phase configuration with the help of SYNCOUT and VEA. An innovative average

current-mode control architecture provides noise immunity and accurate dynamic current sharing during transients. High-

power designs with up to 12A of output current can be enabled with integrated switches using the IC's dual-phase

capability. FC2QFN provides improved thermal and EMI performance. A symmetrical pinout across VIN and PGND further

improves the EMI performance, enabling low-noise designs.

Linear Regulator Output (BIAS)

The devices include a 1.8V linear regulator (VBIAS) that powers the internal circuit blocks. Connect a 2.2μF ceramic

capacitor from BIAS to GND. During startup, the bias regulator draws power from the input and switches over to the output

after the startup is complete (if VOUT > 2.5V). For output voltages less than 1.8V, the bias regulator is always connected

to the input.

System Enable (EN)

An enable control input (EN) activates the devices from their low-power shutdown mode. EN is compatible with input

levels down to 4.5V. EN turns on the internal linear (BIAS) regulator. Once VBIAS exceeds the internal lockout threshold

(VUVBIAS = 1.63V (typ)), the converter activates, and the output voltage ramps up with the programmed soft-start time.

A logic-low at EN shuts down the device. During the shutdown, the BIAS regulator and gate drivers turn off. Shutdown is

the lowest power state and reduces the quiescent current to 4μA (typ). Drive EN high to bring the device out of shutdown.

Synchronization Input (SYNC)

The ADPL12005/ADPL12006 include a SYNC pin, which is a logic-level input used for operating-mode selection and

frequency control. Connecting SYNC to BIAS or to an external clock enables forced fixed-frequency (FPWM) operation.

Connecting SYNC to GND enables automatic skip-mode operation for better light-load efficiency. The ICs synchronize to

an external clock at the rising edge applied at the SYNC pin. The devices synchronize to the external clock in two cycles.

When the external clock signal at SYNC is absent for more than two clock cycles, the devices use the internal clock.

Soft-Start

The devices include an internal 2.5ms (400kHz) and 3.5ms (1.5MHz) soft-start. Soft-start limits startup inrush current by

forcing the output voltage to ramp up towards its regulation point.

Short-Circuit Protection

The devices feature a current limit that protects them against short-circuit and overload conditions at the output. In the

event of a short-circuit or overload condition, the high-side MOSFET remains on until the inductor current reaches the

specified LX current-limit threshold. The converter then turns the high-side MOSFET off and the low-side MOSFET on,

allowing the inductor current to ramp down. Once the inductor current crosses below the current-limit threshold, the

converter turns on the high-side MOSFET again. This cycle repeats until the short or overload condition is removed.

A hard short is detected when the output voltage falls below 25% of the target while in the current limit. If this occurs,

hiccup mode activates, and the output turns off for 35ms at 1.5MHz and 25ms at 400kHz. The output then enters soft-

start and powers back up. This repeats indefinitely while the short circuit is present. Hiccup mode is disabled during soft-

start.