ADPL12005/ADPL12006

20V, 5A/6A Fully Integrated Synchronous Buck

Converters

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Analog Devices | 14

Output Capacitor

Output capacitance is selected to satisfy the output load-transient, output voltage ripple, and closed-loop stability

requirements. During a load step, the output current changes almost instantaneously, whereas the inductor is slow to

react. During this transition time, the load-charge requirements are supplied by the output capacitor, which causes an

undershoot/overshoot in the output voltage. For a buck converter controlled by inductor current, as employed in the

ADPL12005/ADPL12006, output capacitance also affects the control-loop stability.

The output ripple is composed of ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the ESR of the output

capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors,

the entire output ripple is contributed by ΔVESR. Use Equation 8 to calculate the ESR requirement and choose the

capacitor accordingly. If using ceramic capacitors, assume the contribution to the output-ripple voltage from the ESR and

the capacitor discharge to be equal. The following equations show the output capacitance and ESR requirement for a

specified output-voltage ripple.

Equation 8:

ESR =

∆VESR

∆IP-P

COUT =

∆IP-P

8 × ∆VQ × fSW

Where:

∆IP-P =

(

VIN - VOUT) × VOUT

VIN × fSW × L

VOUT_RIPPLE = ∆VESR + ∆VQ

ΔIP-P is the peak-to-peak inductor current as calculated in equation 8, and fSW is the converter’s switching frequency.

The output capacitor supplies the step-load current until the converter responds with a greater duty cycle. The resistive

drop across the output capacitor's ESR and the capacitor discharge causes a voltage droop during a step load. Use a

combination of low-ESR tantalum and ceramic capacitors for better transient load and ripple/noise performance. Keep

the maximum output-voltage deviations below the tolerable limits of the electronics being powered. When using a ceramic

capacitor, assume an 80% and 20% contribution from the output-capacitance discharge and the ESR drop, respectively.

Use the following equations to calculate the required ESR and capacitance value:

Equation 9:

COUT =

∆I

∆V × 2π × fC

Where ΔI is the load change, ΔV is the allowed voltage droop, and fC is the loop crossover frequency, which can be

assumed to be the lesser of fSW/10 or 100kHz. Any calculations involving COUT should consider capacitance tolerance,

temperature, and voltage derating. Table 1 shows the recommended output capacitor values according to switching

frequency and output voltage.

Dual-Phase Operation

Low-IQ Operation in Dual Phase

The ADPL12005/ADPL12006 features dual-phase capability, allowing each IC to be configured as either a controller or a

target. The SYNCOUT pin of the controller outputs a 180-degree out-of-phase clock when SYNC is tied high (FPWM

mode). For low-IQ mode, the SYNC pin of the controller should be pulled low (Skip mode). In this mode, there is no clock

present on the SYNCOUT pin of the controller, and the controller IC enters Skip mode. The internal circuit of the target

IC remains ON during this time and actively looks for the SYNCOUT signal from the controller. Since the target IC is ON,

the quiescent current is slightly higher, even though both of the ICs skip pulses.

To improve the light-load efficiency and further reduce the IQ, the target EN should be pulled low. This disables the target

and its internal circuits, further reducing the IQ. Table 2 summarizes the truth table for low-IQ operations.