-20

-10

0

10

20

30

40

50

60

±2

±1

0

1

2

3

4

5

6

±4

±2

±0

2

4

6

Time (Ps)

VOUT

IOUT

C021

V

OUT

I

OUT

Figure 8-18. 50-mΩ Hot-Short Response Time

8.3 Power Supply Recommendations

The TPS25200 is designed for 2.7 V < VIN < 5 V (typical) voltage rails. While there is a VOUT clamp, it is not

intended to be used to regulate VOUT at approximately 5.4 V with 6 V < VIN < 7 V. This is a protection feature

only.

8.4 Layout

8.4.1 Layout Guidelines

• For all applications, a 0.1-µF or greater ceramic bypass capacitor between IN and GND is recommended as

close to the device as possible for local noise decoupling.

• For output capacitance, refer to Figure 8-3, low ESR ceramic cap is recommended.

• The traces routing the RILIM resistor to the device must be as short as possible to reduce parasitic effects on

the current limit accuracy.

• The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.

8.4.2 Layout Example

Power Ground

4

5

6

2

1

3

OUT

IN

High Frequency

Bypass Capacitor

VIA to Power Ground Plane

ILIM

EN

VI/O

FAULT

Figure 8-19. TPS25200 Board Layout

www.ti.com

TPS25200

SLVSCJ0F – MARCH 2014 – REVISED JULY 2025

Copyright © 2025 Texas Instruments Incorporated

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Product Folder Links: TPS25200