IS43TR16640C datasheet(32/89 Pages) ISSI

32 / 89 page

IS43/46TR16640C, IS43/46TR16640CL

IS43/46TR81280C, IS43/46TR81280CL

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. E

12/27/2024

4.3. AC and DC Logic Input Levels for Differential Signals

4.3.1 Differential signal definition

Figure 4.3.1 Definition of differential ac-swing and “time above ac-level”

4.3.2

Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)

4.3.2.1 Differential AC and DC Input Levels

Symbol

Parameter

DDR3-800, 1066, 1333, 1600, 1866, 2133

unit

Notes

Min

Max

VIHdiff

Differential input logic high

+0.200

Note3

VILdiff

Differential input logic low

Note3

-0.200

VIHdiff(ac)

Differential input high ac

2 x ( VIH(ac) – Vref )

Note3

VILdiff(ac)

Differential input low ac

Note3

2 x ( Vref - VIL(ac) )

Symbol

Parameter

DDR3L-800, 1066, 1333, 1600, 1866, 2133

unit

Notes

Min

Max

VIHdiff

Differential input logic high

+0.180

Note3

VILdiff

Differential input logic low

Note3

-0.180

VIHdiff(ac)

Differential input high ac

2 x ( VIH(ac) – Vref )

Note3

VILdiff(ac)

Differential input low ac

Note3

2 x ( Vref - VIL(ac) )

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs and VREFDQ; if

a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the

respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot

tDVAC

VIH.DIFF.AC.MIN

VIH.DIFF.MIN

VIL.DIFF.MAX

VIL.DIFF.AC.MAX

Half cycle

tDVAC

time

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