Data Sheet

LT83203/LT83205

analog.com

Rev. B

21 of 44

If transient performance is not critical, other passive filter solutions can be realized using a physical inductor as a

larger second L and additional output capacitance for the second C, as shown in Figure 48.

Figure 48. Additional Output Ripple Filtering Using a Second LC Filter

When designing an additional filter for further attenuation of the switching ripple, it is highly recommended to design

with LTpowerCAD® to ensure that the design is stable with a good phase margin and provides sufficient attenuation

at the switching frequency of interest.

The Silent Switcher 3 architecture makes it possible to achieve excellent noise performance from low to high

frequencies at the output of the LT83203/LT83205 while utilizing only passive filtering.

PCB Layout Recommendations

The LT83203/LT83205 is specifically designed to minimize low-frequency (10Hz to 100kHz) noise and EMI emissions

and maximize efficiency when switching at high frequencies. For optimal performance, the LT83203/LT83205 can

use multiple VIN bypass capacitors.

Two small capacitors are placed as close as possible to the LT83203/LT83205 VIN pins, and the third capacitor with a

larger value, 4.7μF or higher, should be placed near one of these two capacitors. For a recommended PCB layout, see

Figure 49.

For more details and PCB design files, refer to the LT83203/LT83205 demo board manual. Note that large, switched

currents flow in the LT83203/LT83205 VIN and GND pins and the input capacitors. The loops formed by the input

capacitors should be as small as possible by placing the capacitors adjacent to the VIN and GND pins. Capacitors with

small case sizes, such as 0402 or 0603, are optimal due to their low parasitic inductance. Special care must be taken

with the input capacitors to ensure they have a low-impedance return path to the IC ground. This is achieved by

placing several grounds through the GND side of the input capacitors such that the ground plane is utilized to full

advantage. This should be an unbroken ground plane with a solid connection to the exposed pad of the IC, as shown

in Figure 49.

LT83203/

LT83205

GND

SW

OUTS

0.47µH

0.1µH

DISCRETE L

100µF

100µF

×6

OPTIONAL

VOUT