6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

I2C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%)(3)

VDD_I2C

Supply range for I2C (SDA/OUT1, SCL/OUT2)

1.65

1.8

3.6

V

VIH

High-level signal voltage

1.05

V

VIL

Low-level signal voltage

0.4

V

VOL

Low-level signal output voltage (open drain)

IOL = –1.6 mA

0.4

V

VBUS_DET IO Pins (Connected to System VBUS signal)

VBUS_THR

VBUS threshold range

See Figure 6-1

2.95

3.30

3.80

V

RVBUS

External resistor between VBUS and VBUS_DET pin

855

887

920

KΩ

RVBUS_PD

Internal pulldown resistance for VBUS_DET

95

KΩ

(1)

VDD must be 3.5 V or greater to advertise 3 A current.

(2)

Internal pullup and pulldown for PORT and ADDR are removed after the device has sampled EN = high or EN_N = low.

(3)

When using 3.3 V for I2C, customer must ensure VDD is above 3.0 V at all times.

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

I2C (SDA, SCL)

tSU:DAT

Data setup time

100

ns

tHD;DAT

Data hold time

10

ns

tSU:STA

Set-up time, SCL to start condition

0.6

µs

tHD:STA

Hold time, (repeated) start condition to SCL

0.6

µs

tSU:STO

Set up time for stop condition

0.6

µs

tBUF

Bus free time between a stop and start condition

1.3

µs

tVD;DAT

Data valid time

0.9

ns

tVD;ACK

Data valid acknowledge time

0.9

ns

fSCL

SCL clock frequency; I2C mode for local I2C control

400

kHz

tr

Rise time of both SDA and SCL signals

300

ns

tf

Fall time of both SDA and SCL signals

300

ns

Cbus_100kHz

Total capacitive load for each bus line when operating at ≤ 100 kHz

400

pF

Cbus_400kHz

Total capacitive load for each bus line when operating at ≤ 400 kHz

100

pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tCCCB_DEFAULT

Power on default of CC1 and CC2 voltage debounce

time

DEBOUCE

register = 2'b00

133

ms

tVBUS_DB

Debounce of VBUS_DET pin after valid VBUS_THR

2

ms

tDRP_DUTY_CYCLE

Power-on default of percentage of time DRP

advertises DFP during a tDRP

DRP_DUTY_CYCLE

register = 2'b00

30%

tDRP

The period during which the TUSB320 or the

TUSB320I in DFP mode completes a DFP to UFP

and back advertisement.

50

75

100

ms

tI2C_EN

Time from TUSB320 EN_N low or TUSB320I EN high

and VDD active to I2C access available

100

ms

tSOFT_RESET

Soft reset duration

26

49

95

ms

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TUSB320, TUSB320I

SLLSEN9F – MAY 2015 – REVISED MARCH 2022

Copyright © 2022 Texas Instruments Incorporated

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