DAC38RF82 datasheet(49/147 Pages) TI2

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DAC38RF82, DAC38RF89

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SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020

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8.3.15 JESD204B Pattern Test

The DAC38RF82 (or DAC38RF89) supports the following test patterns for JESD204B:

•

Link layer test pattern by setting field JESD_TEST_SEQ in register JESD_LN_EN (8.5.45) and monitoring the

lane alarms (1 = fail, 0 = pass)

–

Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)

–

Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)

–

Verify repeating initial lane alignment (ILA) sequence

•

RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an

amount of time to get an estimate of BER.

•

Transport layer test pattern: implements a short transport layer pattern check based on F = 1, 2, 4 or 8. The

short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.

Each sample has a unique value that can be identified with the position of the sample in the user data format.

The sample values are such that correct sample values will never be decoded at the receiver if there is a

mismatch between the mapping formats being used at the transmitter and receiver devices. This can

generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples

being transmitted. Refer to the JESD204B standard section 5.1.6 for more details.

The DAC38RF82 (or DAC38RF89) expects the test samples, in a frame, transmitted by an logic device as per

Table 38:

Table 38. Short Test Patterns

JESD Mode

82121

7CB8, F431

6DA9, E520

n/a

42111

7CB8

F431

n/a

22210

7CB8

F431

n/a

12410

7CB8

F431

n/a

44210

7CB8

F431

6DA9

E520

24410

7CB8

F431

6DA9

E520

41121

7CB8, F431

n/a

81180

7C00, B800, F400, 3100, 6D00,

A900, E500, 2000

n/a

24310

7CB0

F430

6DA0

E520

41380

7CB0, F430, 6DA0, E520, F870,

E960, DA50, CB40

n/a

The short test pattern has duration of one frame period and is repeated continuously for the duration of the test.

Each sample has a unique value that can be identified with the position of the sample in the user data format.

The sample values are such that correct sample values will never be decoded at the receiver if there is a

mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally

be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted.

Following are the steps required to execute the short test functionality in DAC38RF82 (or DAC38RF89).

1. Configure other registers, make sure clocks are up and running.

2. Start driving short test patterns

3. Clear short test alarm by writing ‘0’ to field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP

(8.5.67). This is a paged register, one for each Multi-DUC.

4. Enable short test by writing a ‘1’ to field SHORTTEST_ENA in register MULTIDUC_CFG2 (8.5.14).

5. Read the short test alarm from field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67).

This is a paged register, one for each Multi-DUC

If the alarm read from the register is high, the short test has detected an error.

DAC38RF82 Datasheet(PDF) 49 Page - Texas Instruments

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