DAC38RF82 datasheet(65/147 Pages) TI2

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Fmax

min

PFD

Fvco

Fixed

div x Mdiv

y N

PFD

and

charge pump

Output

buffer

y 4

y M

DAC

CLK

Feedback

High VCO

Low VCO

PLL_N(4-0)

PLL_M(7-0)

DAC38RF82, DAC38RF89

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SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020

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Device Functional Modes (continued)

8.4.3 Internal PLL/VCO

The DAC38RF82 (or DAC38RF89) has an internal clock generation circuit consisting of a PLL and two selectable

VCOs, as shown in Figure 49.

Figure 49. Internal PLL/VCO Block Diagram

DAC38RF82 (or DAC38RF89) each have a low VCO (VCO0) and high VCO (VCO1), but they are tuned to

different center frequencies in each device. The VCO frequency ranges for each device are summarized in

Electrical Characteristics - Digital Specifications. The VCO is selected through field PLL_VCOSEL in register

PLL_CONFIG2 (8.5.81), with ‘0’ selecting the low VCO and a ‘1’ the high VCO. The 7 bit VCO tuning code in

field PLL_VCO in register PLL_CONFIG2 (8.5.81) is used to tune the VCO frequency from the lowest frequency

in the range to the highest frequency for the particular VCO used. For the low VCO the center VCO frequency is

achieved with PLL_VCO = 63decimal and for the high VCO the center frequency is achieved with PLL_VCO =

63decimal.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field

PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15decimal initially for 18 mA

supply current in the VCO and ~1.4 VPP single ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4

frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating

frequency of the phase-frequency detector (PFD) and charge pump (CP) requires this. The M (feedback) clock

divider takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-

bit field in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to

÷256, and is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to

÷1, ÷2 and ÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum

operating frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum

allowable M divider ratio.

(18)

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD

operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio

range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

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