DM505LRBABF datasheet(195/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

EDMA controller uses the shared MMU1 module for transfering to and from DSP module. This

provides several benefits including:

•

Protection of Host CPU memory regions from accidental corruption by EDMA TPTCs.

•

Direct allocation of buffers in user space without the need for translation between CPU and DSP

applications using EDMA TPTCs.

Accesses by the EDMA TPTCs (both TPTC0 and TPTC1) may optionally be routed through the

MMU1.

The TPTC0 and TPTC1 routing allows EDMA transfer controller to be used to perform transfers using

only the virtual addresses of the associated buffers.

For more information chapter Enhanced DMA of the device TRM.

6.10 Peripherals

6.10.1 VIP

The VIP module provides video capture functions for the device. VIP incorporates a multichannel raw

video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)

engine to store incoming video in various formats. The device uses a single instantiation of the VIP

module giving the ability of capturing up to two video streams.

A VIP module includes the following main features:

•

Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which

has two video input ports, Port A and Port B, where Port A can be configured as a 16/8-bit port, and

Port B is a fixed 8-bit port.

•

Each video Port A can be operated as a port with clock independent input channels (with interleaved or

separated Y/C data input). Embedded sync and external sync modes are supported for all input

configurations.

•

Support for a single external asynchronous pixel clock, up to 165MHz per port.

•

Pixel Clock Input Domain Port A supports up to one 16-bit input data bus, including BT.1120 style

embedded sync for 16-bit data.

•

Embedded Sync data interface mode supports single or multiplexed sources

•

Discrete Sync data interface mode supports only single source input

•

16-bit data input plus discrete syncs can be configured to include:

–

8-bit YUV422 (Y and U/V time interleaved)

–

16-bit YUV422 (CbY and CrY time interleaved)

–

16-bit RGB565

–

16-bit RAW Capture

•

Discrete sync modes include:

–

VSYNC + HSYNC (FID determined by FID signal pin or HSYNC/VSYNC skew)

–

VSYNC + ACTVID + FID

–

VBLANK + ACTVID (ACTVID toggles in VBLANK) + FID

–

VBLANK + ACTVID (no ACTVID toggles in VBLANK) + FID

•

Multichannel parser (embedded syncs only)

–

Embedded syncs only

–

Pixel (2x or 4x) or Line multiplexed modes supported

–

Performs demultiplexing and basic error checking

–

Supports maximum of 9 channels in Line Mux (8 normal + 1 split line)

DM505LRBABF Datasheet(PDF) 195 Page - Texas Instruments

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