DM505LRBABF datasheet(224/295 Pages) TI2

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224

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

•

PMIC component DM and guidelines should be referenced for the following:

–

Routing remote feedback sensing to optimize per each SMPS’s implementation

–

Selecting power filtering capacitor values and PCB placement.

•

Max Total Effective Resistance (Reff) budget can range from 4 – 100mΩ for key Device power rails not

including ground returns depending upon maximum load currents and maximum DC voltage drop

budget (as discussed above).

•

Max Device supply input voltage difference budget of 5mV under max current loading shall be

maintained across all balls connected to a common power rail. This represents any voltage difference

that may exist between a remote sense point to any power input.

•

Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high

frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending

upon maximum transient load currents.

•

Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device

including ground returns are as follows:

–

+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~

200kHz)

–

+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)

•

Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output

power filter node including ground return is determined by applying the Frequency Domain Target

Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly

designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general

regions of interest as can be seen in Figure 7-14.

–

1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response

characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very

low due to power filtering and bulk capacitor values when PDN has very low trace resistance (i.e.

good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over

this low frequency range. This will ensure that a max transient current event will not cause a

voltage drop more than the PMIC’s current step response can support (typ 3%).

–

2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.

parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase

with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly

increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient

current event will not cause a voltage drop to be more than 5% of the min supply voltage.

DM505LRBABF Datasheet(PDF) 224 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 224 Page - Texas Instruments

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