DM505LRBABF datasheet(228/295 Pages) TI2

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228

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Table 7-4 illustrates the approved and validated power supply connections to the Device for the SMPS

outputs of the TPS65917 and LP8732 combined with LP8733 PMICs.

Table 7-4. Power Supply Connections

TPS65917

Dual Converter Solution

Valid Combination 1:

SMPS1

LP8733Q Buck0

vdd_dspeve

SMPS2

LP8733Q Buck1

vdd

SMPS3

LP8732Q Buck0

vdds18v, vdds18v_ddr[3:1], vddshv[6:1]

SMPS4

LP8732Q Buck1

vdds_ddr1, vdds_ddr2, vdds_ddr3

Table 7-5 illustrates the LP8733 and LP8732 OTP IDs required for DM50x processor systems using

different DDR memory types.

Table 7-5. OTP ID Memory Types Support

DDR Type

LP8733Q

LP8732Q

OTP Version

DDR2

LPDDR2

DDR3

DDR3L

7.3.6

DPLL Voltage Requirement

The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage

inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The

TPS65917 PMIC LDOLN output or LDO0 on LP8733Q dual power solution is specifically designed to

meet this low noise requirement.

NOTE

For more information about Input Voltage Sources, see DPLLs, DLLs Specifications

Table 7-6 presents the voltage inputs that supply the DPLLs.

Table 7-6. Input Voltage Power Supplies for the DPLLs

POWER SUPPLY

DPLLs

vdda_per

DPLL_PER and PER HSDIVIDER analog power supply

vdda_ddr_dsp

DPLL_DSP, DPLL_DDR and DDR HSDIVIDER analog power supply

vdda_gmac_core

GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER analog power

supply

7.3.7

Loss of Input Power Event

A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for

a “Loss of Input Power” event are:

•

“Loss of Input Power” early warning

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using the 1st Stage

Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the 2nd Stage

PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different 1st Stage Converter is used,

care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided that

can disable 2nd Stage PMIC to begin a controlled and compliant SoC power down sequence. The

total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage reaches minimum

level of 2.75V should be minimum of 1.5ms and 2ms preferred.

DM505LRBABF Datasheet(PDF) 228 Page - Texas Instruments

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