DM505LRBABF datasheet(229/295 Pages) TI2

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229

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

•

Maximize discharge time of 1st Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load

switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3V IO load

current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to

maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down

sequence. Care should be taken to either disable or isolate any additional peripheral components

that may be loading the VSYS_3V3 rail as well.

•

Sufficient bulk decoupling capacitance on the 1st Stage Vout (VSYS_3V3 per PDN) that allows for

desired 1.5 – 2ms elapsed time as described above.

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200uF of total

capacitance on VSYS_3V3. The 1st Stage Converter (i.e. LM536033-Q1) can typically drive a max

of 400uF to help extend VSYS_3V3 discharge time for a compliant SoC power down sequence.

•

Optimizing the 2nd Stage SoC PMIC’s OTP settings that determines SoC power up and down

sequences and total elapsed time needed for a controlled sequence.

–

TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per

the SCH and components used. The definition of these OTPs is captured in the detailed timing

diagrams for both power up and down sequences. The PDN diagram typically shows a

recommended PMIC OTP ID based upon the SoC and DDR memory types.

7.3.8

Example PCB Design

The following sections describe an example PCB design and its resulting PDN performance for the

vdd_dspeve key processor power domain.

NOTE

Materials presented in this section are based on generic PDN analysis on PCB boards and

are not specific to systems integrating the Device.

7.3.8.1

Example Stack-up

Layer Assignments:

•

Layer Top: Signal and Segmented Power Plane

–

Processor and PMIC components placed on Top-side

•

Layer 2: Gnd Plane1

•

Layer 3: Signals

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Layer n: Power Plane1

•

Layer n+1: Power Plane 2

•

Layer n+2: Signal

•

Layer n+3: Gnd Plane2

•

Layer Bottom: Signal and Segmented Power Planes

–

Decoupling caps, etc.

Via Technology: Through-hole

Copper Weight:

•

½ oz for all signal layers.

•

1-2oz for all power plane for improved PCB heat spreading.

7.3.8.2

vdd_dspeve Example Analysis

Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not

exceed 33mΩ per Table 7-3 and (7).

DM505LRBABF Datasheet(PDF) 229 Page - Texas Instruments

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