DM505LRBABF datasheet(233/295 Pages) TI2

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D+

S = 2 W = 200 µm

SPRS91v_PCB_SE_GND_01

233

DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.4

Single-Ended Interfaces

7.4.1

General Routing Guidelines

The following paragraphs detail the routing guidelines that must be observed when routing the various

functional LVCMOS interfaces.

•

Line spacing:

–

For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the

crosstalk between switching signals between the different lines. On the PCB, this is not achievable

everywhere (for example, when breaking signals out from the device package), but it is

recommended to follow this rule as much as possible. When violating this guideline, minimize the

length of the traces running parallel to each other (see Figure 7-18).

Figure 7-18. Ground Guard Illustration

•

Length matching (unless otherwise specified):

–

For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length

difference between the longest and the shortest lines) must be less than 25 mm.

–

For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length

difference between the longest and the shortest lines) must be less than 2.5 mm.

•

Characteristic impedance

–

Unless

otherwise

specified,

the

characteristic

impedance

for

single-ended

interfaces

recommended to be between 35-Ω and 65-Ω.

•

Multiple peripheral support

–

For interfaces where multiple peripherals have to be supported in the star topology, the length of

each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify

signal integrity based on simulations including actual PCB extraction.

7.4.2

QSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the QSPI

interfaces.

7.4.2.1

If QSPI is operated in Mode 0 (POL=0, PHA=0):

•

The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.

•

The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must

be approximately equal to the signal propagation delay from the QSPI device CLK pin to the

qspi1_rtclk ball (C to D).

•

The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be

approximately equal to the signal propagation delay of the control and data signals between the QSPI

device and the SoC device (E to F, or F to E).

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