DM505LRBABF datasheet(237/295 Pages) TI2

237 / 295 page

Device

rtc_osc_xo

rtc_osc_xi_clkin32

Crystal

(Optional)

SPRS91v_PCB_CLK_OSC_02

237

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Table 7-11. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)

PARAMETER

TYPICAL VALUE

UNIT

Operating speed

1500

Mbps

UI (bit time)

667

Intralane skew

Have to satisfy mode-conversion S parameters(1)

Interlane skew (UI / 50)

13.34

PCB lane-to-lane skew (0.1 UI)

66.7

(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22

7.5.2.1.3 Frequency-domain Specification Guidelines

After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D

Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and

compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance

Specification for D-PHY Version v1-01-00_r0-03.

If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design

needs to be improved.

7.6

Clock Routing Guidelines

7.6.1

Oscillator Ground Connection

Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in

the ground plane causes a voltage drop in the ground. Figure 7-21 shows the grounding scheme for slow

(low frequency) clock generated from the internal oscillator.

Figure 7-21. Grounding Scheme for Low-Frequency Clock

Figure 7-22 shows the grounding scheme for high-frequency clock.

DM505LRBABF Datasheet(PDF) 237 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 237 Page - Texas Instruments

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