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DM505LRBABF Datasheet(PDF) 241 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 241 Page - Texas Instruments |
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241 / 295 page  241 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated 7.7.3.2 Compatible JEDEC LPDDR2 Devices Table 7-14 shows the supported LPDDR2 device configurations which are compatible with this interface. Table 7-14. Compatible JEDEC LPDDR2 Devices (Per Interface) NO. PARAMETER CONDITION MIN MAX UNIT 1 JEDEC LPDDR2 device speed grade tc(DDR_CK) and tc(DDR_NCK) LPDDR2-667 2 JEDEC LPDDR2 device bit width x16 x32 Bits 3 JEDEC LPDDR2 device count 1 1 Devices 7.7.3.3 LPDDR2 PCB Stackup Table 7-15 shows the minimum stackup requirements. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint. Table 7-15. Six-Layer PCB Stackup Suggestion LAYER TYPE DESCRIPTION 1 Signal Top signal routing 2 Plane Ground 3 Signal Signal routing 4 Plane Split power plane 5 Plane Ground 6 Signal Bottom signal routing PCB stackup specifications for LPDDR2 interface are listed in Table 7-16. Table 7-16. PCB Stackup Specifications NO. PARAMETER MIN TYP MAX UNIT 1 PCB routing and plane layers 6 2 Signal routing layers 3 3 Full ground reference layers under LPDDR2 routing region(1) 1 4 Full vdds_ddr power reference layers under the LPDDR2 routing region(1) 1 5 Number of reference plane cuts allowed within LPDDR2 routing region(2) 0 6 Number of layers between LPDDR2 routing layer and reference plane(3) 0 7 PCB routing feature size 4 mils 8 PCB trace width, w 4 mils 9 PCB BGA escape via pad size(4) 18 20 mils 10 PCB BGA escape via hole size 8 mils 11 Single-ended impedance, Zo(5) 50 75 Ω 12 Impedance control(6)(7) Zo-5 Zo Zo+5 Ω (1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (2) No traces should cross reference plane cuts within the LPDDR2 routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation. (3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape. (5) Zo is the nominal singled-ended impedance selected for the PCB. (6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter. (7) Tighter impedance control is required to ensure flight time skew is minimal. |
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