DM505LRBABF datasheet(238/295 Pages) TI2

238 / 295 page

ddr1_ck

ddr1_nck

SPRS917_LPDDR2_01

xi_oscj

vssa_oscj

Device

xo_oscj

Crystal

(Optional)

SPRS91v_PCB_CLK_OSC_03

238

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

(1)

j in *_osc = 0 or 1

Figure 7-22. Grounding Scheme for High-Frequency Clock

7.7

LPDDR2 Board Design and Layout Guidelines

7.7.1

LPDDR2 Board Designs

TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 7-12

and Figure 7-23.

Table 7-12. Switching Characteristics for LPDDR2 Memory Interface

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CK)

Cycle time, ddr1_ck and ddr1_nck

7.52

3.00(1)

(1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The

device has only been tested per the limits published in this table.

Figure 7-23. LPDDR2 Memory Interface Clock Timing

7.7.2

LPDDR2 Device Configurations

There is signal device configuration supported, supporting either 32b or 16b data widths. Table 7-13 lists

all the supported configuration.

Table 7-13. Supported LPDDR2 Device Combinations

NUMBER OF LPDDR2

DEVICES

LPDDR2 DEVICE WIDTH (BITS)

MIRRORED?

LPDDR2 EMIF WIDTH (BITS)

32 / 16

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