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DM505LRBABF Datasheet(PDF) 234 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 234 Page - Texas Instruments |
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234 / 295 page  A B C D E F qspi1_sclk qspi1_rtclk R2 R2 R1 QSPI device clock input QSPI device IOx, CS# qspi1_d[x], qspi1_cs[y] 0 * Ω 10 Ω 10 Ω Locate both R2 resistors close together near the QSPI device SPRS906_PCB_QSPI_01 234 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated • The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip) • 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-19. • Propagation delays and matching: – A to C = C to D = E to F – Matching skew: < 60pS – A to B < 450pS – B to C = as small as possible (<60pS) Figure 7-19. QSPI Interface High Level Schematic Mode 0 (POL=0, PHA=0) NOTE *0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for finetuning if needed. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1): • The qspi1_rtclk input can be left unconnected. • The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be approximately equal to the signal propagation delay of the control and data signals between the QSPI device and the SoC device (E to F, or F to E). • The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be < 450pS (~7cm as stripline or ~8cm as microstrip). • 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-20. |
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