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DM505LRBABF Datasheet(PDF) 230 Page - Texas Instruments

Part # DM505LRBABF
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505LRBABF Datasheet(HTML) 230 Page - Texas Instruments

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Buck0 (3A)
L1402
0.47uH, 4A, 2520
DFE252012PD-R47M
DM50x
VDD_DSPEVE
LP8733 PMIC
SPRS977_PCB_CORE_02
Buck 0_SW
_
(22,23)
VPO_S1_SW
VPO_S1_AVS
C1409
22uF, 6.3V, X7R, 1206
GCM31CR70J226ME23
FB_B0
(2)
U1401
R1010
10mOhm, 1210
INA226&
Power Bench
U5000
C5079, 5080, 5085,
5100, 5101, 5111
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C5021
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C5019
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C5018
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C5037
2.2uF, 6.3V, X5R, 0603
C1005X5R0J225M
C5030
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
C5026
22uF, 6.3V, X7R, 1206
GCM31CR70J226ME23
VDD_DSPEVE_AVS
(P12, P11, M9, P9,
K8, L8, P8)
FB_VPO_S1_AVS
230
DM505
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com
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Applications, Implementation, and Layout
Copyright © 2016–2018, Texas Instruments Incorporated
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.5nH per Table 7-3 and (7) (ESL NOT included).
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 54mΩ per Table 7-3 and (7).
Table 7-7. Example PCB vdd_dspeve PI Analysis Summary
Parameter
Recommendation
Example PCB
OPP
OPP_NOM
Clocking Rate
500 MHz
Voltage Level
1 V
1 V
Max Current Draw
1 A
1 A
Max Effective Resistance: Power
Inductor Segment Total Reff
13 mΩ
11.4mΩ
Max Loop Inductance
< 2.5 nH
0.73 - 1.58 nH
Impedance Target
54 mΩ for F < 20 MHz
28.8 mΩ for F < 20MHz
Figure 7-15 shows a PCB layout example and the resulting PI analysis results.
Figure 7-15. vdd_dspeve Simplified SCH Diagram



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