DM505LRBABF datasheet(239/295 Pages) TI2

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32-Bit LPDDR2

Device

0.1 µF

32-Bit LPDDR2

Interface

ddr1_d[31:0]

ddr1_dqm[3:0]

ddr1_dqs[3:0]

ddr1_dqsn[3:0]

ZQ0/1

Vref(CA)

Vref(DQ)

ddr1_ecc_d[7:0]

ddr1_dqm_ecc

ddr1_dqs_ecc

ddr1_dqsn_ecc

1 K

vdds_ddr

0.1 µF

1 K

DDR_VREF

SPRS917_LPDDR2_02

RDAT

ddr1_ck

ddr1_nck

ddr1_cke0

ddr1_csn0

RCA

ddr1_rasn (ddr1_ca0)

(1)

ddr1_casn (

(1)

ddr1_ca1)

ddr1_wen (ddr1_ca2)

(1)

ddr1_a13 (ddr1_ca3)

(1)

ddr1_a10 (ddr1_ca4)

(1)

ddr1_a1 (ddr1_ca5)

(1)

ddr1_a2 (ddr1_ca6)

(1)

ddr1_ba0 (ddr1_ca7)

(1)

ddr1_ba1 (ddr1_ca8)

(1)

ddr1_ba2 (ddr1_ca9)

(1)

RCA

DQ[31:0]

DM[3:0]

DQS_t[3:0]

CK_t

CK_c

CKE

CS_n

CA[0]

CA[1]

CA[2]

CA[3]

CA[4]

CA[5]

CA[6]

CA[7]

CA[8]

CA[9]

DQS_c[3:0]

1 K

vdds_ddr

1 K

vdds_ddr

239

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.7.3

LPDDR2 Interface

7.7.3.1

LPDDR2 Interface Schematic

Figure 7-24 shows the schematic connections for 32-bit interface with or without ECC using one x32

LPDDR2 device.

Figure 7-24. 32-Bit Interface with and without ECC using one x32 LPDDR2 device(1)(3)(4)

(1) When LPDDR2 memory are used, these signal function as ddr1_ca[9:0]. For more information, see Table 4-9, EMIF1 Signal

Descriptions

(2) Rca is 10

Ω resistor and is to be placed near DM50x device.

(3) The RDAT is 22 Ω resistor and is to be placed near DM50x device

(4) If ECC is required, pins available behind data lane 3 (data would then only use 16bit (lanes 1 and 2))

When not using a part of LPDDR2 interface (using x16 or not using the LPDDR2 interface):

•

Connect the vdds_ddr supply to 1.8 V

•

Tie off ddr1_dqsx (x=0,1,2,3) that are unused to vss via 1 k

Ω

•

Tie off ddr1_dqsnx (x=0,1,2,3) that are unused to vdds_ddr via 1 k

Ω

•

All other unused pins can be left as NC.

DM505LRBABF Datasheet(PDF) 239 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 239 Page - Texas Instruments

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