DM505LRBABF datasheet(243/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

7.7.3.6

LPDDR2 Net Classes

Table 7-18. Clock Net Class Definitions for the LPDDR2 Interface

CLOCK NET CLASS

PIN NAMES

ddr1_ck and ddr1_nck

DQS0

ddr1_dqs0 and ddr1_dqsn0

DQS1

ddr1_dqs1 and ddr1_dqsn1

DQS2

ddr1_dqs2 and ddr1_dqsn2

DQS3

ddr1_dqs3 and ddr1_dqsn3

Table 7-19. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface

SIGNAL NET CLASS

ASSOCIATED CLOCK

NET CLASS

BALL NAMES

ADDR_CTRL

ddr1_ba[2:0], ddr1_csn0, ddr1_cke0, ddr1_rasn, ddr1_casn, ddr1_wen,

ddr1_a1, ddr1_a2, dr1_a10, ddr1_a13

DQ0

DQS0

ddr1_d[7:0], ddr1_dqm0, ddr1_dqs0, ddr1_dqsn0 (1)

DQ1

DQS1

ddr1_d[15:8], ddr1_dqm1, ddr1_dqs1, ddr1_dqsn1 (1)

DQ2

DQS2

ddr1_d[23:16], ddr1_dqm2, ddr1_dqs2, ddr1_dqsn2 (1)

DQ3

DQS3

ddr1_d[31:24], ddr1_dqm3, ddr1_dqs3, ddr1_dqsn3 (1)

(1) DQ data class includes DQS/N pins

7.7.3.7

LPDDR2 Signal Termination

On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for

normal operation. System designers may evaluate the need for additional series termination if required

based on signal integrity, EMI and overshoot/undershoot reduction.

On board series termination is recommended for all ADDR_CTRL and CK class signals. It is

recommended a resistor with value of 10

Ω to be placed close to the DM50x source pin (within 350 mils).

On board series termination is recommended for all DQx and DQSx class signals. It is recommended a

resistor with value of 22

Ω to be placed close to the DM50x source pin (within 500 mils).

7.7.3.8

LPDDR2 DDR_VREF Routing

DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory. DDR_VREF is

intended to be half the LPDDR2 power supply voltage and is typically generated with a voltage divider

connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1-

µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate

routing congestion.

7.7.4

Routing Specification

7.7.4.1

DQS[x] and DQ[x] Routing Specification

DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 7-27 and

Figure 7-28 represent the supported topologies. Figure 7-29 and Figure 7-30 show the DQS[x] and DQ[x]

routing. Figure 7-31 shows the DQLM for the LPDDR2 interface.

DM505LRBABF Datasheet(PDF) 243 Page - Texas Instruments

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