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DM505LRBABF Datasheet(PDF) 242 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 242 Page - Texas Instruments |
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242 / 295 page  LPDDR2 ADDT_CTRL LPDDR2 DATA SPRS917_LPDDR2_05 LPDDR2 Keepout Region Encompasses Entire LPDDR2 Routing Area Y X1 SPRS917_LPDDR2_04 LPDDR2 DATA LPDDR2 ADDT_CTRL 242 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated 7.7.3.4 LPDDR2 Placement Figure 7-25 shows the placement rules for the device as well as the LPDDR2 memory device. Placement restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing space. Figure 7-25. Placement Specifications Table 7-17. Placement Specifications(1) NO. PARAMETER MIN MAX UNIT 1 X1 Offset(2)(3) 900 mils 2 Y Offset 200 mils 3 Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5) 4 w (1) LPDDR2 keepout region to encompass entire LPDDR2 routing area. (2) Measurements from center of device to center of LPDDR2 device. (3) Minimizing X1 and Y improves timing margins. (4) w is defined as the signal trace width. (5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground plane. 7.7.3.5 LPDDR2 Keepout Region The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2 keepout region is defined for this purpose and is shown in Figure 7-26. This region should encompass all LPDDR2 circuitry and the region size varies with component placement and LPDDR2 routing. Non- LPDDR2 signals should not be routed on the same signal layer as LPDDR2 signals within the LPDDR2 keepout region. Non-LPDDR2 signals may be routed in the region provided they are routed on layers separated from LPDDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground or vdds_ddr power plane in this region. In addition, the vdds_ddr power plane should cover the entire keepout region. Figure 7-26. LPDDR2 Keepout Region |
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