TLC6989DYYR datasheet(36/71 Pages) TI2

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7.6.3 CCSICTRL Register (Address = 0x2) [Reset = 0x0000]

CCSICTRL is shown in Figure 7-25 and described in Table 7-7.

Return to the DEVICE Registers Summary Table.

Figure 7-25. CCSICTRL Register

RESERVED

CCSI_SS_CLKO

R/W-0x0

RESERVED

CCSI_DATA_RATE

R/W-0x0

Table 7-7. CCSICTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

RESERVED

R/W

0x0

Reserved

9-8

CCSI_SS_CLKO

R/W

0x0

Spread spectrum setting for CLK_O pin

0x0 = disabled

0x1 = 2%

0x2 = 4%

0x3 = 8%

7-4

RESERVED

R/W

0x0

Reserved

3-0

CCSI_DATA_RATE

R/W

0x0

Data rate for CCSI

0x0 = 1Mbit/s

0x1 = 1.25Mbit/s

0x2 = 1.43Mbit/s

0x3 = 1.67Mbit/s

0x4 = 2Mbit/s

0x5 = 2.22Mbit/s

0x6 = 2.5Mbit/s

0x7 = 2.86Mbit/s

0x8 = 3.33Mbit/s

0x9 = 4Mbit/s

0xA = 5Mbit/s

0xB = 6.67Mbit/s

0xC = 8Mbit/s

0xD = 10Mbit/s

0xE = 13.33Mbit/s

0xF = 20Mbit/s

TLC6989

SLVSHF5 – NOVEMBER 2024

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