Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099

Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com

Characteristic Data and Specifications are subject to change without notice.

©2007 Mimix Broadband, Inc.

Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept

their obligation to be compliant with U.S. Export Laws.

August 2007 - Rev 16-Aug-07

Mimix Broadband’s 30.0-46.0 GHz GaAs MMIC receiver has a noise

figure of 3.5 dB and 18.0 dB image rejection across the band. This

device is a three stage LNA followed by an image reject resistive

pHEMT mixer and includes an integrated LO doubler and LO buffer

amplifer. The image reject mixer eliminates the need for a bandpass

filter after the LNA to remove thermal noise at the image frequency.

The use of integrated LO doubler and LO buffer amplifier makes the

provision of the LO easier than for fundamental mixers at these

frequencies. I and Q mixer outputs are provided and an external 90

degree hybrid is required to select the desired sideband. This MMIC

uses Mimix Broadband’s 0.15 µm GaAs PHEMT device model

technology, and is based upon electron beam lithography to ensure

high repeatability and uniformity. The chip has surface passivation to

protect and provide a rugged part with backside via holes and gold

metallization to allow either a conductive epoxy or eutectic solder die

attach process. This device is well suited for Millimeter-wave

Point-to-Point Radio, LMDS, SATCOM and VSAT applications.

30.0-46.0 GHz GaAs MMIC

Receiver

Page 1 of 7

Sub-harmonic Receiver

Integrated LNA, LO Doubler/Buffer, Image Reject Mixer

+4.0 dBm Input Third Order Intercept (IIP3)

+2.0 dBm LO Drive Level

9.0 dB Conversion Gain

3.5 dB Noise Figure

18.0 dB Image Rejection

100% On-Wafer RF, DC and Noise Figure Testing

100% Visual Inspection to MIL-STD-883 Method 2010

Features

General Description

Absolute Maximum Ratings

Supply Voltage (Vd)

Supply Current (Id1,2), (Id3)

Gate Bias Voltage (Vg)

Input Power (RF Pin)

Storage Temperature (Tstg)

Operating Temperature (Ta)

Channel Temperature (Tch)

+6.0 VDC

110, 180 mA

+0.3 VDC

+5 dBm

-55 to MTTF Table

MTTF Table

Chip Device Layout

(3) Channel temperature affects a device's MTTF. It is

recommended to keep channel temperature as low as

possible for maximum life.

3

3

Units

GHz

GHz

GHz

GHz

dB

dB

dBm

dBc

dB

dB

dBm

VDC

VDC

VDC

mA

mA

Min.

35.0

30.0

15.5

DC

-

-

-

-

-

-

-

-

-1.2

-1.2

-

-

Typ.

-

-

-

-

10.0

9.0

+2.0

18.0

3.5

40.0/40.0

+4.0

+4.0

-0.3

-0.5

50

145

Max.

46.0

46.0

25.0

4.0

-

-

-

-

-

-

-

+5.5

+0.1

+0.1

100

165

Parameter

Frequency Range (RF) Upper Side Band

Frequency Range (RF) Lower Side Band

Frequency Range (LO)

Frequency Range (IF)

Input Return Loss RF (S11)

Small Signal Conversion Gain RF/IF (S21)

Image Rejection

Noise Figure (NF)

Isolation LO/RF @ LOx1/LOx2

Input Third Order Intercept (IIP3)

Drain Bias Voltage (Vd1,2,3)

Gate Bias Voltage (Vg1,2,3)

Gate Bias Voltage (Vg4,5) Mixer, Doubler

Supply Current (Id1,2) (Vd1,2=4.0, Vg=-0.3V Typical)

Supply Current (Id3) (Vd3=4.0V,Vg=-0.3V Typical)

(1) Measured using constant current.

(2) Measured using LO Input drive level of 0.0 and +2.0 dBm.

1,2

2

2

2

R1004-BD