AFE10004RGETEP datasheet(49/159 Pages) TI2

49 / 159 page

Terminate read operations by issuing a not-acknowledge condition at the end of the last byte to be read. Figure

6-22 shows that for single-byte operation, the controller must leave the SDA line high during the acknowledge

time of the first byte that is read from the target.

Target Address

RegAddr[7:0]

Target Address

Data[7:0]

From Controller to Target

From Target to Cntroller

Figure 6-22. I2C Single-Byte Read Access Protocol

Block access functionality is provided to minimize the transfer overhead of large data sets. Block access enables

multibyte transfers and is configured by setting bit 7 of the register address high. Figure 6-23 and Figure 6-24

show that until the transaction is terminated by the STOP condition, the device reads and writes the subsequent

memory locations. If the controller reaches address 0x7E in a page, the device continues reading and writing

from this address until the transaction is terminated.

Target Address

RegAddr[6:0]

Data[7:0]

From Controller to Target

From Target to Controller

Data[7:0]

Address of the First Register of

the contiguous memory block

Data to First Register

N bytes of data to

contiguous memory

locations following

First Register

Figure 6-23. I2C Block Write Access

Target Address

RegAddr[6:0]

Target Address

Data[7:0]

From Controller to Target

From Target to Controller

Data[7:0]

Address of the First Register of

the contiguous memory block

Data to First Register

N bytes of data to

contiguous memory

locations following

First Register

Figure 6-24. I2C Block Read Access

6.5.1.5 I2C Timeout Function

The device resets the serial interface if either SCL or SDA are held low for 25ms (typical) between a START

and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START

condition. To avoid activating the timeout function, maintain a communication speed of at least 1kHz for the SCL

operating frequency.

6.5.1.6 I2C General-Call Reset

The device supports reset using the two-wire general call address 00h (0000 0000b). The device acknowledges

the general-call address, and responds to the second byte. If the second byte is 06h (0000 0110b), the device

executes a software reset. This software reset initiates a reset event. The device takes no action in response to

other values in the second byte.

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AFE10004-EP

SLASFM1A – JUNE 2025 – REVISED DECEMBER 2025

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