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AFE10004RGETEP Datasheet(PDF) 9 Page - Texas Instruments |
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AFE10004RGETEP Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 159 page ![]() 5.6 Timing Requirements all minimum and maximum specifications at TJ = –55℃ to +125℃ and all typical specifications at TJ = 25℃, VDD = 4.5V to 5.5V, VIO = 1.65V to 3.6V, positive output range: VCC = 4.5V to 5.5V, VSS = GND, negative output range: VSS = –11V to –4.5V, VCC = GND, and DAC outputs unloaded (unless otherwise noted) MIN NOM MAX UNIT I2C TIMING REQUIREMENTS f(SCL) I2C clock frequency 10 400 kHz t(LOW) SCL clock low period 1.3 µs t(HIGH) SCL clock high period 0.6 µs t(HDSTA) Hold time after repeated start condition. After this period, the first clock is generated 0.6 µs t(SUSTA) Repeated start condition setup time 0.6 µs t(SUSTO) Stop condition setup time 0.6 µs t(BUF) Bus free time between stop and start condition 1.3 µs t(SUDAT) Data setup time 100 ns t(HDDAT) Data hold time 0 900 ns tF,SDA Data fall time 20 300 ns tF,SCL Clock fall time 300 ns tR,SCL Clock rise time 300 ns tR,SCL100 Rise time for SCL ≤ 100kHz 1000 ns SCL and SDA timeout 20 30 ms SPI TIMING REQUIREMENTS, VIO = 2.7V to 3.6V f(SCLK) SPI clock frequency 20 MHz t(SCLKLOW) Clock high time 20 ns t(SCLKHIGH) Clock low time 20 ns t(SDISU) Data setup time 10 ns t(SDIHD) Data hold time 10 ns t(SDODLY) SDO delay 0 20 ns t(SDODIS) SDO disable 0 20 ns t(CSSU) CS setup 10 ns t(CSHD) CS hold 20 ns t(CSHIGH) CS pulse-width 25 ns SPI TIMING REQUIREMENTS, VIO = 1.65V to 2.7V f(SCLK) SPI clock frequency 10 MHz t(SCLKLOW) Clock high time 40 ns t(SCLKHIGH) Clock low time 40 ns t(SDISU) Data setup time 10 ns t(SDIHD) Data hold time 10 ns t(SDODLY) SDO delay 0 30 ns t(SDODIS) SDO disable 0 30 ns t(CSSU) CS setup 10 ns t(CSHD) CS hold 20 ns t(CSHIGH) CS pulse-width 25 ns www.ti.com AFE10004-EP SLASFM1A – JUNE 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: AFE10004-EP |
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