24LC024 datasheet(6/41 Pages) MICROCHIP

6 / 41 page

24AA024/24LC024/24AA025/24LC025

DS20001210Q-page 6

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2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

2.1

Chip Address Inputs (A0, A1, A2)

The A0, A1 and A2 inputs are used by the 24AA024/

24LC024/24AA025/24LC025

for

multiple

device

operation. The levels on these inputs are compared

with the corresponding bits in the client address. The

chip is selected if the comparison is true. Up to eight

devices (four for SOT-23 package) may be connected

to the same bus by using different Chip Select bit

combinations. These inputs must be connected to

either VCC or VSS. In most applications, the chip

address inputs A0, A1 and A2 are hard-wired to logic ‘0’

or logic ‘1’. For applications in which these pins are

controlled by a microcontroller or other programmable

device, the chip address pins must be driven to logic ‘0’

or logic ‘1’ before normal device operation can

proceed.

2.2

Serial Address/Data Input/Output

(SDA)

SDA is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open-drain

terminal; therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 k

 for 100 kHz and 2 k for

400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.3

Serial Clock (SCL)

The SCL input is used to synchronize the data transfer

from and to the device.

2.4

Write-Protect (WP) (24XX024 Only)

WP is the hardware write-protect pin. It must be tied to

VCC or VSS. If tied to Vcc, hardware write protection is

enabled. If WP is tied to Vss, the hardware write

protection is disabled. Note that the WP pin is available

only on the 24XX024. This pin is not internally

connected on the 24XX025.

2.5

Noise Protection

The 24AA024/24LC024/24AA025/24LC025 employs a

VCC threshold detector circuit which disables the

internal erase/write logic if the VCC is below 1.5V at

nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

Name

PDIP

SOIC

TSSOP

DFN/TDFN(1)

MSOP

SOT-23

Description

Address Pin AO

Address Pin A1

—

Address Pin A2

VSS

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

—

Write-Protect Input

VCC

Power Supply

Note 1: Exposed pad on DFN/TDFN can be connected to VSS or left floating.

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