W150

Rev 1.0, November 24, 2006

Page 12 of 14

Layout Example

Duty Cycle

Measured on rising and falling edge at

1.5V

45

55

45

55

%

Output Skew

Measured on rising and falling edge at

1.5V

250

250

ps

Propagation Delay

Measured from SDRAMIN

3.7

3.7

ns

AC Output Impedance

Average value during switching

transition. Used for determining series

termination value.

15

15

48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008

MHz

Deviation from 48 MHz

(48.008 – 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

2

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

2

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached within 1 ms from

power-up. Short cycles exist prior to frequency stabili-

zation.

3ms

AC Output Impedance

Average value during switching transition. Used for deter-

mining series termination value.

25

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

f

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

24.004

MHz

Deviation from 24 MHz (24.004 – 24)/24

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/34 = 24.004 MHz)

57/34

Output Rise Edge Rate Measured from 0.4V to 2.4V

0.5

2

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

2

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

45

55

%

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached within 1 ms from

power-up. Short cycles exist prior to frequency stabili-

zation.

3ms

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

25

SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)

Parameter

Description

Test Condition/Comments

CPU = 66.8 MHz

CPU = 100 MHz

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.