W150

Rev 1.0, November 24, 2006

Page 3 of 14

Overview

The W150 was designed as a single-chip alternative to the

standard two-chip Intel 440BX AGPset clock solution. It

provides sufficient outputs to support most single-processor,

four SDRAM DIMM designs.

Functional Description

I/O Pin Operation

Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon

power-up these pins act as logic inputs, allowing the determi-

nation of assigned device functions. A short time after

power-up, the logic state of each pin is latched and the pins

become clock outputs. This feature reduces device pin count

by combining clock outputs with input select pins.

An external 10-k

“strapping” resistor is connected between

Figure 2 show two suggested methods for strapping resistor

connections.

Upon W150 power-up, the first 2 ms of operation are used for

input logic selection. During this period, the five I/O pins (2, 8,

9, 29, 30) are three-stated, allowing the output strapping

resistor on the l/O pins to pull the pins and their associated

capacitive clock load to either a logic HIGH or LOW state. At

the end of the 2-ms period, the established logic “0” or “1”

condition of the l/O pin is latched. Next the output buffer is

enabled, converting the l/O pins into operating clock outputs.

It should be noted that the strapping resistors have no signif-

icant effect on clock output signal integrity. The drive

impedance of clock output (< 40 , nominal) is minimally

affected by the 10-k

series termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

to minimize system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input

period, the corresponding specified output frequency is

has not yet reached full value, output frequency initially may

has stabilized. In either case, a short output clock cycle may

be produced from the CPU clock outputs when the outputs are

enabled.

VDDQ2

50, 56

P

Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or

3.3V.

GND

4, 10, 23,

26, 34,

42, 48, 53

G

Ground Connections: Connect all ground pins to the common system ground plane.

Pin Name

Pin No.

Pin

Type

Pin Description

Power-on

Reset

Timer

Output Three-state

Data

Latch

Hold

QD

W150

Clock Load

10 k

Output

Buffer

(Load Option 1)

10 k

(Load Option 0)

Output

Low

Output Strapping Resistor

Series Termination Resistor

Figure 1. Input Logic Selection Through Resistor Load Option