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PCI11010C Datasheet(PDF) 36 Page - Microchip Technology

Part # PCI11010C
Description  PCIe Switch with Integrated Ethernet MAC and Programmable I/O
PDF  46 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PCI11010C Datasheet(HTML) 36 Page - Microchip Technology

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2025 Microchip Technology Inc. and its subsidiaries
DS00006232A-page 36
PCI11010C
4.4
AC Specifications
This section details the various AC timing specifications of the device.
4.4.1
POWER SEQUENCE TIMING
Power supplies must adhere to the following rules:
• All power supplies of the same voltage must be powered up/down together.
• There is no power-up sequencing requirement. However all power supplies must reach operational levels within
the time periods specified in Table 4-2.
• There is no power-down sequencing or timing requirement, however the device must not be powered for an
extended period of time without all supplies at operational levels.
• Following initial power-on, or if a power supply brownout occurs (i.e., one or more supplies drops below opera-
tional limits), a power-on reset must be executed once all power supplies reach operational levels.
• Do not drive input signals without power supplied to the device.
4.4.2
PCIE TIMING
All device PCIe signals (
PCIE_xx) conform to the voltage, power, and timing characteristics/specifications as set forth
in the PCI Express Base Specification Revision 3.1a. Please refer to the PCI Express Base Specification Revision 3.1a
for additional information.
4.4.3
SMBUS TIMING
All device SMBus signals (
SMBUS_xx) conform to the voltage, power, and timing characteristics/specifications as set
forth in the System Management Bus Specification Revision 2.0. Please refer to the System Management Bus Specifi-
cation, Version 2.0 for additional information. Additionally, when operating at 1 MHz, the SMBus signals confirm to the
timing characteristics/specifications as set forth in the System Management Bus Specification Revision 3.0. Please refer
to the System Management Bus Specification, Version 3.0 for additional information.
4.4.4
UART TIMING
All device UART signals (
UART_xx) conform to the timing characteristics/specifications as set forth in the RS-232,
RS-422 and RS-485 specifications. Please refer to the RS-232, RS-422 and RS-485 specifications for additional infor-
mation.
4.4.5
SPI CONTROLLER TIMING
This section specifies the SPI controller (
SPI_CTRL[0:1]_xx) timing requirements for the device. The SPI controllers
support operation at 30, 20, 15, 12, 10 or 2 MHz.
Note: Violation of these specifications may damage the device.
FIGURE 4-1:
POWER SEQUENCE TIMING
TABLE 4-2:
POWER SEQUENCE TIMING
Symbol
Description
Min
Typ
Max
Unit
tpon
Power supply turn-on time
0
—
5
ms
All Power Supply Pins
tpon



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