VT1616 6-Channel AC97 Codec with S/PDIF
Revision 1.5, October 11, 2002
20
Data Sheet
Extended Audio Status/Control Register (Index 2Ah)
PRx
Multi-channel Output Control
All three bits, PRK, PRJ, PRI behave similarly. When set to “0”, the respective DAC(s) is (are)
turnedon. PRK is for LFE, PRJ for Surround(Rear pair), PRI for Center channel.
SPCV
S/PDIF Configuration Valid (Read Only)
“0” : S/PDIF configuration (SSA, SSR, DAC rate, DRS) invalid(not supported)
“1” : S/PDIF configuration (SSA, SSR, DAC rate, DRS) valid(supported)
xDAC
Multi-channel Output Status (Read Only)
These readonly bits, LDAC, SDAC, CDAC behave similarly. When they report “1”, the respective
DAC(s), LFE, SurroundandCenter is (are) ready.
SSA[1:0]
S/PDIF Slot Assignment
These bits determine the S/PDIF data source from AC-link slot selection when SPDIF_OUT, pin 48
is low during reset (pulled low by external application circuit). If the S/PDIF application circuit is
not implemented, these bits will return only 0. The default state reflects the pervasive design feature
of common AC’97 digital controllers supporting slots 3 & 4. Slots 10 & 11 are expected to be used
in the future to support concurrent 6 channels analog and2 channel digital audio (compressedor
LPCM).
SPDIF
Sony/Philips Digital Audio Interface Enable/Disable
“1” :
Set this bit to turn on the S/PDIF transmitter.
“0” :
The S/PDIF transmitter is off by default.
VRA
Variable Sampling Rate Mode control
“1” :
Enable VSR
“0” :
Fixed48 KHz sampling rate
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
–
–
PRK
PRJ
PRI
SPCV
–
LDAC SDAC CDAC SSA1 SSA0
–
SPDIF
–
VRA
3800h
SSA1
SSA0
S/PDIF Source Data
0
0
AC-link slots 3 & 4 (front stereo pair, power-up default)
0
1
AC-link slots 7 & 8 (surroundpair)
1
0
AC-link slots 6 & 9 (LFE & Center pair)
1
1
AC-link slots 10 &11
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