© 2005 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FST3125 • Rev. 1.0.3

6

Physical Dimensions

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X 45°

1

0.10

C

C

B

CA

7

M

14

B

A

8

SEE DETAIL A

5.60

0.65

1.70

1.27

8.75

8.50

7.62

6.00

4.00

3.80

(0.33)

1.27

0.51

0.35

1.75 MAX

1.50

1.25

0.25

0.10

0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

R0.10

0.50

0.25

Figure 6. 14-Lead, Small-Outline Integrated Circuit (SOIC) 0.150-inch Narrow

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the warranty therein, which covers Fairchild products.

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