AD4086 datasheet(31/91 Pages) AD

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Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 31 of 91

OVERVIEW

The AD4086 digital interface consists of a 4-wire SPI for device

configuration, four general-purpose input and output (GPIO) pins,

a conversion data access interface with selectable output format

(LVDS or SPI data interface), and a conversion start input (CNV+

and CNV−) that can be configured for LVDS or CMOS level signal-

ing.

ADC CONVERSION CONTROL

The ADC acquires a sample and initiates a conversion operation on

the rising edge of the convert start signal, applied at the CNV+ and

CNV− pins. There are two possible configurations for the electrical

signaling at the convert start input pins: CMOS or LVDS.

CMOS is the default mode on power-up and after reset. CMOS

requires that the CNV− pin be tied to the digital interface ground

(IOGND). In this mode, the convert signal must be a CMOS logic

signal referenced to IOGND and applied at CNV+, with logic levels

according to the parameters of the digital inputs (CNV, GPIOx,

DCS, and DCLK) in Table 1.

To switch to LVDS mode, the LVDS_CNV_EN bit of the ADC Data

Interface Configuration B register (see the ADC Data Interface Con-

figuration B Register section, Address 0x16) must be set to 1. In

this mode, an external 100Ω termination resistor must be installed

between the CNV+ and CNV− pins, as close to the AD4086 as

possible. In LVDS mode, the CNV+ and CNV− pins must be driven

differentially with an LVDS driver conforming to the levels specified

in the LVDS I/O (EIA-644) parameters in Table 1. Care must be

taken to closely match the CNV+ and CNV− differential signal pair

routing and to use controlled impedance to ensure signal integrity.

SPI REGISTER INTERFACE

The configuration register interface is an SPI that enables both

device configuration and system status monitoring. This interface

is configured for 4-wire, full-duplex operation. Dedicated interface

pins for the interface chip select (CS), serial clock (SCLK), and

serial data input (SDI) are intended for direct connection to the host

controller. By default, at power-up or after a software reset, the

configuration interface SDO function is enabled and assigned to the

GPIO0 pin.

The configuration interface timing convention implemented in this

design is consistent with SPI Mode 3, clock polarity (CPOL) =

1, clock phrase (CPHA) = 1. As such, the serial clock (SCLK) is

expected to idle high, and the state of the data pins, SDI and SDO,

are updated on the falling (leading) edge of the clock, such that

these pins can be sampled on the subsequent rising (trailing) edge.

See the Analog Dialogue article, Introduction to SPI Interface, for

more details regarding the SPI and SPI modes.

The memory access controller associated with this interface sup-

ports a number of user-programmable options accessible through

the interface configuration memory space (Address 0x00 to Ad-

dress 0x11). The available options for the AD4086 are listed and

described in Table 14.

Table 14. Configuration Memory Controller Options Summary

Interface Option

Description

Software Reset (SW_RESET,

SW_RESETX)

Resets the internal configuration memory to the default state (except for ADDR_ASCENSION bit). Data FIFO is unaffected. Only use this

reset method once the ADC is in an idle state, where conversions are not clocked, and any existing conversion is completed. See the

Software Reset section for details.

Address Ascension

(ADDR_ASCENSION)

Selecting this option changes the behavior of the memory controller address counter from decrementing (default) to incrementing. This

change affects multibyte transfers, for example, when accessing a multibyte register as a single entity or when streaming mode is enabled.

The selection impacts the starting address for multibyte register accesses in strict register access mode. See the Address Ascension

Selection section for details.

Short Instruction

(SHORT_INSTRUCTION)

Selecting this option reduces the length of the address field in the instruction word from 15 bits to 7 bits.

Single Instruction

(SINGLE_INST)

Selecting this option changes from the default streaming mode to single instruction mode, which requires the host controller to transmit an

instruction for each register access within a given SPI frame. The size of an entity is dependent on the strict register access setting and

whether or not the register is multibyte. This feature allows random access to the memory space during configuration. See the Instruction

Mode Selection section for details.

Strict Register Access

(STRICT_REGISTER_ACCESS)

Selecting this option instructs the memory controller to treat a multibyte register as a single entity, generating a fault when a partial access

is attempted. See the Strict Access Selection and Multibyte Registers section for details.

CRC Enable (CRC_ENABLE,

CRC_ENABLEB)

Selecting this option enables a cyclic redundancy check (CRC) to verify the integrity of data sent to and received from the host. See the

Configuration Cyclical Redundancy Check (CRC) section for details.

Status Data Transmission

(SEND_STATUS)

Selecting this options enables the transmission of status data through the SDO line during the instruction phase of the data frame. See

theStatus Data Transmission section for details.

Loop Count (LOOP_COUNT)

Sets the data byte count before looping to the start address. When streaming data, a nonzero value sets the number of data bytes written

before the address loops back to the start address. A maximum of 255 bytes can be written using this approach. A value of 0x00 disables

the loop back so that addressing wraps around at the upper and lower limits of the memory. After writing this register, the loop value applies

only to the following SPI instruction and auto clears upon the end of that instruction.

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