AD4086 datasheet(32/91 Pages) AD

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Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 32 of 91

ADC CONVERSION DATA INTERFACE

Two signaling format options are available to access conversion

results:

►

LVDS level signaling (LVDS data interface)

►

CMOS level signaling (SPI data interface)

The choice of interface is usually determined by the requirements

and constraints of the application at hand. For example, if contin-

uous fast data acquisition is required, then the LVDS signaling

interface is typically the preferred option. If the application requires

only noncontinuous bursts of data acquisitions, then either the

LVDS or the SPI data interfaces can be used. The capabilities of

the digital interface host can also determine which interface option

is chosen.

Common to both the LVDS and SPI data interfaces are the follow-

ing flexible features that reduce the burden on the chosen digital

host:

►

Multilane data transfer: enables sustained data throughput at

reduced interface clock speeds.

►

Test pattern generation: facilitates interface integrity checks.

Additionally, for the LVDS only, there is the option to set a configu-

rable output drive.

By default, the LVDS interface is selected on power-up and after a

reset. As can be seen in Figure 50, for LVDS, the data path of the

ADC results is routed though the offset and gain correction block

where there is the option for the following:

►

Continuously read, directly, the raw ADC conversion results.

►

Continuously read the ADC results processed by a user-selected

digital filter (see the Digital Filter section for details).

►

Read up to 16k unfiltered results from the FIFO.

►

Read up to 16k digitally filtered results from the FIFO.

Figure 50. LVDS Data Interface Options

If configured for the SPI data interface, as can be seen in Figure 51,

the available data paths are as follows:

►

Read up to 16k unfiltered results from the FIFO.

►

Read up to 16k digitally filtered results from the FIFO.

Figure 51. SPI Data Interface Data Path Options

Additional features specific to the selected interface format are also

available and are described in the LVDS Data Interface section and

the SPI Data Interface section.

SPI CONFIGURATION INTERFACE

All serial transactions between the system host and the AD4086

configuration registers are executed using the configuration SPI.

Each serial transaction consists of at least one instruction phase

during which the desired memory operation, that is, read or write,

and the starting address for the transaction are transmitted to the

AD4086. The instruction phase is immediately followed by a data

transaction phase during which one or more bytes of information

is exchanged between the host and the AD4086. This content is

framed by a continuous assertion of the interface chip select (CS )

as illustrated in the generic timing presented in Figure 52 and

Figure 53.

Figure 52. Generic SPI Configuration Frame, CRC Disabled

Figure 53. Generic SPI Configuration Write Operation, CRC Enabled

AD4086 Datasheet(PDF) 32 Page - Analog Devices

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