LM3661 datasheet(12/17 Pages) NSC

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Circuit Operation

The LM3661 operates as follows: During the first part of

each switching cycle, the control block in the LM3661 turns

on the internal PFET switch. This allows current to flow from

the input through the inductor to the output filter capacitor

and load. The inductor limits the current to a ramp with the

slope of (V

IN −VOUT)/L, by storing energy in a magnetic field.

During the second part of each cycle, the controller turns the

PFET switch off, blocking current flow from the input, and

then turns the NFET synchronous rectifier on. In response,

the inductor’ magnetic field collapse, generating a voltage

that forces current from ground through the synchronous

rectifier to the output filter capacitor and load. As the stored

energy is transferred back into the circuit and depleted, the

inductor current ramps down with a slope of V

OUT/L. If the

inductor current reaches zero before the next cycle, the

synchronous rectifier is turned off to prevent current reversal.

The output filter capacitor stores charge when the inductor

current is high, and release it when low, smoothing the

voltage across the load.

PWM Operation

The LM3661 can be set to current-mode PWM operation by

connecting the SYNC/MODE pin to V

DD. While in PWM

(Pulse Width Modulation) mode, the output voltage is regu-

lated by switching at a constant frequency and then modu-

lating the energy per cycle to control power to the load.

Energy per cycle is set by modulating the PFET switch

on-time pulse-width to control the peak inductor current. This

is done by controlling the PFET switch using a flip-flop driven

by an oscillator and a comparator that compares a ramp

from the current-sense amplifier with an error signal from a

voltage-feedback error amplifier. At the beginning of each

cycle, the oscillator sets the flip-flop and turns on the PFET

switch, causing the inductor current to ramp up. When the

current sense signal ramps past the error amplifier signal,

the PWM comparator resets the flip-flop and turns off the

PFET switch, ending the first part of the cycle. The NFET

synchronous rectifier turns on until the next clock pulse or

the inductor current ramps to zero. If an increase in load

pulls the output voltage down, the error amplifier output

increases, which allows the inductor current to ramp higher

before the comparator turns off the PFET switch. This in-

creases the average current sent to the output and adjusts

for the increase in the load. Before going to the PWM com-

parator, the current sense signal is summed with a slope

compensation ramp from the oscillator for stability of the

current feedback loop. During the second part of the cycle, a

zero crossing detector turns off the NFET synchronous rec-

tifier if the inductor current ramps to zero.

LDO Operation

Connecting the SYNC/MODE pin to GND sets the LM3661

in Linear Mode operation. While in Linear mode (LDO) the

device consumes only 29 µA (typ.) quiescent current for

system standby operation. It is capable of delivering up to

15 mA. This is done by using an internal pass transistor and

an error amplifier to sense the output voltage and maintain

the desire output voltage. During LDO mode, the PFET and

NFET of the network switch off to reduce quiescent current.

Frequency Synchronization

The SYNC/MODE input can also be used for frequency

synchronization. To synchronize the LM3661 to an external

clock, supply a digital signal to the SYNC/MODE pin with a

voltage swing exceeding 0.4V to 1.2V. During synchroniza-

tion, the LM3661 initiates cycles on the rising edge of the

clock. When synchronized to an external clock, it operates in

PWM mode. The device can synchronize to an external

clock over frequencies from 500 kHz to 750 kHz. Use the

following waveform and duty-cycle guidelines when applying

an external clock to the SYNC/MODE pin. The duty cycle

can be between 30% and 70%. Clock under/overshoot

should be less than 100 mV below GND or above V

DD.

When applying noisy clock signals, especially sharp edged

signals from a long cable during evaluation, terminate the

cable at its characteristic impedance; add an RC filter to the

SYNC/MODE pin, if necessary, to soften the slew rate and

20098803

FIGURE 2. Typical Operating Circuit

LM3661 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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