FT232BM datasheet(46/54 Pages) FTDI

Part #	FT232BM

Description	Dual USB UART / FIFO I.C.

PDF	54 Pages

Scroll/Zoom	100%

Manufacturer	FTDI [Future Technology Devices International Ltd.]

Direct Link	http://www.ftdichip.com

Logo

46 / 54 page

DS2232C Version 1.2

Page 46 of 54

FT2232C Dual USB UART / FIFO I.C.

OSC

A15..A8

AD7..0

ALE

CS#

WR#

High Address

Low Address

Data

t9 t10

t11

IORDY

Figure 29 - MCU Host Bus Emulation Mode Signal Timing - Write Cycle

Time

Description

High address byte is placed on the bus if the extended write is used.

Low address byte is put out.

1 clock period for address is set up.

ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is low.

ALE goes low to latch address and CS# is set active low.

Data driven onto the bus.

1 clock period for data setup.

WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.

WR# is driven inactive high.

t10

CS# is driven inactive, 1/2 a clock period after WR# goes inactive

t11

Data is held until this point, and may now change

FT232BM Datasheet(PDF) 46 Page - Future Technology Devices International Ltd.