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AFE8221RFP Datasheet(PDF) 13 Page - Texas Instruments |
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AFE8221RFP Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 48 page ![]() www.ti.com CONTROL INTERFACE SPI Interface CS SCK MOSI MISO INSTRUCTI N O DATA 1 0 0 REG_ADDR 0 7 8 15 14 13 12 11 10 9 6 5 4 3 2 1 1 0 1 MEM MEM_ADDR 0 7 8 15 14 13 12 11 10 9 6 5 4 3 2 1 AFE8221 SBAS394A – APRIL 2007 – REVISED MARCH 2008 The second 16 bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for Configuration and control data are written to the a read cycle. AFE8221 via the control interface. The control interface supports two protocols, SPI and I2C. If the Figure 5 shows an SPI write cycle. The cycle is CTRL_MODE pin is tied low, then an SPI interface is initiated by the high-to-low transition of the CS line. implemented. If CTRL_MODE is tied high, then an 32 SCK pulses clock the instruction and the data into I2C protocol-compatible interface is implemented. the MOSI line. Data are clocked in MSB first. The first 16 bits are the instruction. There are two possible write cycle instructions: register write and memory write. The formats for these instructions are shown in The SPI interface consists of four signals: a serial Figure 6 and Figure 7, respectively. clock (SCK), an active-low chip select (CS), a serial data input (MOSI—master out, slave in), and a serial The only information required for a register write is data output (MISO—master in, slave out). Data are the seven-bit register address (REG_ADDR). For a transferred in groups of 32 bits. The first 16 bits are memory write, both the five-bit memory select (MEM) the instruction, which indicates: plus the six-bit memory address (MEM_ADDR) are required. 1. If data are to be written or to be read; 2. If the data target is a register or RAM; and Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write 3. The address of the data target. cycle, this data word is written to the appropriate register or memory location in the AFE8221. NOTE: To terminate a Write/Read cycle, CS must be brought high. Figure 5. SPI Control Interface Write Cycle Figure 6. Register Write Instruction Format Figure 7. Memory Write Instruction Format Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): AFE8221 |
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