AFE8221RFP datasheet(19/48 Pages) TI

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IF ADC ALARM/ATTENUATOR

QUADRATURE MIXER/NCO

I=ADC

cos(2 ft+

)

(1)

Q=ADC

sin(2 ft+

)

(2)

f=f

MCLK

ddc0_demod_freq

(3)

ddc0_demod_phase

(4)

DIGITAL DOWNCONVERTER 0 (DDC0)

AFE8221

SBAS394A – APRIL 2007 – REVISED MARCH 2008

Table 4. DDC Control Register Settings

PARAMETER

ADDRESS

BITS

The output of each IF ADC is monitored to ensure

ddc0_cic_dec_rate

8:0

that the full-scale input range is not exceeded. If an

ADC over-range condition occurs, an overflow signal

ddc0_cic_scale

11:6

is generated that may be used to generate an

ddc0_cic_shift

5:0

interrupt on the IRQ line, depending on the settings in

ddc0_demod_freq[31:16]

15:0

the IRQ interrupt generator.

ddc0_demod_freq[15:0]

15:0

In addition, programmable limits may be set for each

ddc0_demod_phase[31:16]

15:0

IF ADC. If the absolute value of IF_ADC0 exceeds

ddc0_demod_phase[15:0]

15:0

if_adc_limit0 or the absolute value of IF_ADC1

ddc0_fir1_base_address

13:8

exceeds ifadc_limit1, then an interrupt may be

generated on IRQ again depending on the settings in

ddc0_fir1_mode

1:0

the IRQ interrupt generator.

ddc0_fir1_ncoeffs

7:2

ddc0_fir1_nodec

In the case of an IF ADC event, the IRQ status

ddc0_fir2_nodec

event and on which ADC channel it occurred. The

ddc0_fir2a_base_address

15:9

IRQ status register can be polled to determine if an IF

ddc0_fir2a_mode

1:0

ADC event has occurred in the case where IF ADC

ddc0_fir2a_ncoeffs

8:2

events are masked from generating an interrupt.

ddc0_fir2a_shift

3:0

The

control

variable

ddc0_atten

causes

ddc0_fir2b_base_address

15:9

attenuation of the IF_ADC0 output prior to the DDC.

ddc0_fir2b_mode

1:0

The attenuation ranges in 3dB steps from 0dB (for

ddc0_fir2b_ncoeffs

8:2

ddc0_atten = 0) to –18dB (for ddc0_atten = 6).

ddc1_atten has the same effect on the output of

ddc0_fir2b_shift

7:4

IF_ADC1.

ddc0_interleave

In order to better synchronize the IF ADC attenuator

ddc_en[0]

with the tuner automatic gain control (AGC), a delay

ddc_sync

may be programmed between when a new value of

ddc_atten is written and when it takes effect. When a

new value of ddc0_atten is written, a counter (driven

by MCLK) is initialized to ddc0_delay. When the

The NCO frequency and initial phase are set by the

counter reaches zero, the actual attenuation change

32-bit unsigned

variables

ddc0_demod_freq

and

occurs. Likewise, ddc1_delay affects ddc1_atten.

ddc0_demod_phase. The I and Q outputs of the

Note that if a new ddc0_atten is written before the

mixer

can

calculated

Equation

and

delay counter has reached zero from the previous

Equation 2.

write, the previous write is discarded. Table 3 shows

the attenuator, delay, and limit control variables.

Table 3. IF ADC Control Register Settings

where ADC is the output of the IF analog-to-digital

converter, f is the NCO phase offset (in radians)

PARAMETER

ADDRESS

BITS

given by Equation 3, and

φ is the NCO phase offset

ddc0_atten

2:0

(in radians) given by Equation 4.

ddc1_atten

2:0

ddc0_delay

15:0

ddc1_delay

15:0

ifadc_limit0

11:0

ifadc_limit1

11:0

DDC0 operation is controlled by ddc_en[0]. When

ddc_en[0] is '1', operation of DDC0 is enabled. If

ddc_en[0] is '0', operation of DDC0 is disabled.

Table 4 shows the DDC0 operation control settings.

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