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WM8941 Datasheet(PDF) 70 Page - Wolfson Microelectronics plc |
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WM8941 Datasheet(HTML) 70 Page - Wolfson Microelectronics plc |
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70 / 96 page  WM8941 Pre Production w PP, Rev 3.3, December 2007 70 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits. Figure 42 3-Wire Serial Control Interface READBACK IN 3-WIRE MODE The following two timing diagrams are also supported. Figure 43 Alternative 3-Wire Serial Control Timing Figure 44 Alternative 3-Wire Serial Control Timing A limited number of Readback addresses are provided to enable ALC operation to be monitored and to establish the identity and revision of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 Software Reset 15:0 CHIP_ID Readback the CHIP ID R1 Power Management 1 2:0 DEVICE_REVI SON Readback the DEVICE_REVISON Table 57 Readback Registers |
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