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WM8956 Datasheet(PDF) 52 Page - Wolfson Microelectronics plc |
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WM8956 Datasheet(HTML) 52 Page - Wolfson Microelectronics plc |
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52 / 80 page  WM8956 Preliminary Technical Data w PTD, July 2007, Rev 2.1 52 SYSCLK (=MCLK OR PLL OUTPUT) (MHz) DACDIV DAC SAMPLE RATE (kHz) 000 (=1) 48 001 (=1.5) 32 010 (=2) 24 011 (=3) 16 100 (=4) 12 101 (=5.5) (Not used) 110 (=6) 8 12.288 111 Reserved 000 (=1) 44.1 001 (=1.5) (Not used) 010 (=2) 22.05 011 (=3) (Not used) 100 (=4) 11.025 101 (=5.5) 8.018 110 (=6) (Not used) 11.2896 111 Reserved 000 (=1) 8 001 (=1.5) (Not used) 010 (=2) (Not used) 011 (=3) (Not used) 100 (=4) (Not used) 101 (=5.5) (Not used) 110 (=6) (Not used) 2.048 111 Reserved Table 32 DAC Sample Rates When operating in slave mode, the host device must provide sufficient BCLK cycles to transfer complete data words to the DACs. Table 33 shows the maximum word lengths supported for a given SYSCLK and BCLKDIV, assuming that the DACs are running at maximum rate (i.e. DACDIV[2:0]=000). |
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