WM8956 datasheet(64/80 Pages) WOLFSON

64 / 80 page

WM8956

Preliminary Technical Data

PTD, July 2007, Rev 2.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

3:0

BCLKDIV[3:0]

0000

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 to 1111 = SYSCLK / 32

Clocking and

Sample Rates

8:7

Reserved

ALRCGPIO

GPIO1 Pin Function Select

0 = GPIO pin function disabled

1 = GPIO pin function enabled

General

Purpose Input /

Output;

Digital Audio

Interface

WL8

8-Bit Word Length Select (Used with

companding)

0 = Off

1 = Device operates in 8-bit mode.

Audio Interface

Control

4:3

DACCOMP[1:0]

DAC companding

00 = off

01 = reserved

10 = µ-law

11 = A-law

Audio Interface

Control

R9 (09h)

Audio

Interface

2:0

000

Reserved

DACVU

N/A

DAC Volume Update

Writing a 1 to this bit will cause left and right

DAC volumes to be updated (LDACVOL and

RDACVOL)

Output Signal

Path

R10 (0Ah)

Left DAC

Volume

7:0

LDACVOL[7:0]

11111111

Left DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

Output Signal

Path

DACVU

N/A

DAC Volume Update

Writing a 1 to this bit will cause left and right

DAC volumes to be updated (LDACVOL and

RDACVOL)

Output Signal

Path

R11 (0Bh)

Right DAC

Volume

7:0

RDACVOL[7:0]

11111111

Right DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

Output Signal

Path

R12 (0Ch)

8:0

000000000

Reserved

R13 (0Dh)

8:0

000000000

Reserved

R14 (0Eh)

8:0

000000000

Reserved

WM8956 Datasheet(PDF) 64 Page - Wolfson Microelectronics plc

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