WM8956 datasheet(59/80 Pages) WOLFSON

59 / 80 page

Preliminary Technical Data

WM8956

PTD, July 2007, Rev 2.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLL_EN

PLL Enable

0 = Power down

1 = Power up

LMIC

Left Input PGA Enable

0 = Power down

1 = Power up

(Note: PGA also requires AINL to be set)

RMIC

RIght Input PGA Enable

0 = Power down

1 = Power up

(Note: PGA also requires AINR to be set)

LOMIX

Left Output Mixer Enable

0 = Power down

1 = Power up

R47 (2Fh)

Power

Management

(3)

ROMIX

Right Output Mixer Enable

0 = Power down

1 = Power up

Table 39 Power Management

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8956, the master clock may be

stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In

Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.

However, since setting DIGENB has no effect on the power consumption of other system

components external to the WM8956, it is preferable to disable the master clock at its source

wherever possible.

MCLK should not be stopped while the class D outputs are enabled, as this would prevent the

outputs from functioning.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0 = Master clock enabled

1 = Master clock disabled

Table 40 Enabling the Master Clock

NOTE: Before DIGENB can be set, the control bits DACL and DACR must be set to zero and a

waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs

from re-starting correctly.

SAVING POWER AT HIGHER SUPPLY VOLTAGE

The AVDD supply of the WM8956 can operate beteen 2.7V and 3.6V. By default, all analogue

circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply

voltages down to 2.7V. At lower voltages, performance can be improved by increasing the bias

current by setting VSEL[1:0] = 01. If low power operation is preferred the bias current can be left at

the default setting. This is controlled as shown below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional

Control (1)

7:6

VSEL

[1:0]

Analogue Bias Optimisation

00 = Reserved

01 = Increased bias current, optimized for

AVDD=2.7V

1X = Lowest bias current, optimized for

AVDD=3.3V

Table 41 Bias Optimisation

WM8956 Datasheet(PDF) 59 Page - Wolfson Microelectronics plc

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