8 / 19 page
W311
Document #: 38-07703 Rev. **
Page 8 of 19
Byte 9: System Reset and Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
PCI_DRV
0
PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5
Reserved
0
Reserved
Bit 4
RST_EN_WD
0
This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 3
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
WD_TO_STATU
S
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1
WD_EN
0
0 = Stop and re-load Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note:
W311 will generate system reset, reload a recovery frequency, and lock
itself into a recovery frequency mode after a watchdog timer time-out occurs.
Under recovery frequency mode, W311 will not respond to any attempt to
change output frequency via the SMBus control bytes. System software can
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.
Bit 0
Reserved
0
Reserved
Byte 10: Skew Control Register
Bit
Name
Default
Description
Bit 7
CPU_Skew2
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6
CPU_Skew1
0
Bit 5
CPU_Skew0
0
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
AGP_Skew1
0
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0
AGP_Skew0
0
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
